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BT8110/8110B
High-Capacity ADPCM Processor
This specification describes the BT8110 and BT8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding and decoding. The fixed-rate coding algorithms include those specified in ANSI Standard T1.303-1989. These algorithms are identical to those in ITU-T Recommendations G.726 and G.727. These circuits also implement the variable-rate or embedded codes specified in ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. A single ADPCM processor integrated circuit can provide 24 or 32 full-duplex channels of ADPCM processing (encoding and decoding). In some applications, two circuits can be combined to provide 48 or 64 full-duplex channels. Both A-law and -law PCM translations are provided. Interface options such as serial and parallel inputs and outputs, along with hardware and microprocessor control modes, are provided by the integrated circuits. Up to 14 separate ADPCM algorithms are available in any given configuration on a per-channel basis. The BT8110 requires an external lookup table ROM. The BT8110B has an internal lookup table ROM, or can use an external lookup table ROM. When in direct framer interface mode, transparent channels in the BT8110 will operate at 56 kbit/s; the BT8110B operates at 64 kbit/s. A hardware control, direct framer interface mode has been added to the BT8110B. For more details on the BT8110B mode controls, refer to Table 1-1 and Table 1-4.
Distinguishing Features
* * BT8110B offers internal ROM 24 or 32 full-duplex channel capacity (48 or 64 channels with two processors) 2-, 3-, 4- and 5-bit quantization dynamically selectable on a channel-by-channel, frame-by-frame basis Transparent channel operation Two control modes available: microprocessor and hardware. Direct framer interface for both T1 and E1 signal formats Supports the optimal RESET function described in the algorithm standards Supports even-bit inversion of A-law inputs and outputs (required by ITU-T Recommendations G.726, and G.727) Minimum throughput delay Pin compatible with BT8110 8 mw per-channel, low-power CMOS
*
* * * * *
* * *
Functional Block Diagram
Applicable Standards
* * * * * * ANSI T1.302-1987 ANSI T1.303-1989 ANSI T1.310-1991 ITU-T G.726, G.727 ANSI T1.501-1994 ANSI T1Y1 Technical Reports #3 and #10
64 Kbit/s PCM Input
Convert to Uniform PCM ENCODER
Input Signal
+
+
-
Difference Signal
Adaptive Quantizer
Signal Estimate Reconstructed Signal
32 Kbit/s ADPCM Output
Adaptive Predictor
+
Quantized Difference Signal
Inverse Adaptive Quantizer
Applications
* * *
64 Kbit/s PCM Output
32 Kbit/s ADPCM Input
Inverse Adaptive Quantizer DECODER
Quantized Difference Signal
+
+
Reconstructed Signal Convert to
PCM
-
Signal Estimate
Synchronous Coding Adjustment
Adaptive Predictor
* * * * * *
T1/E1 Transcoders T1/E1 Multiplexers Personal Communications Systems: Digital European Cordless Telecommunications (DECT), Personal Access Communications System (PACS) Wireless Local Loop Voice PairGain DCME Systems Speech Processing/Recording Voice Mail/Packetization Voice over ATM/Frame Relay
Data Sheet
100060C January 2000
Ordering Information
Model Number BT8110EPJ BT8110EPJB Package 68-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) Ambient Temperature Range -40 C to +85 C -40 C to +85 C
Revision History
Revision A B C Level Advanced December 1996 January 2000 The timing diagrams for the following figures have been updated: Figure 2-3, Figure 2-5, Figure 2-6, Figure 2-7, Figure 2-8, Figure A-2, Figure A-3, Figure A-4. Date Created Description
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100060C
Conexant
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Channel Capacity and Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.1.1 1.1.2 1.1.3 1.2 Signal Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Embedded Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 2.1.2 2.1.3 2.2 2.2.1 Clocking and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 24- or 32-Channel Full-Duplex Interleaved Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1.1 Signal Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1.2 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48- or 64-Channel Encoder-Only Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48- or 64-Channel Decoder-Only Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.4 2.4.1 2.4.2
2-5 2-6 2-8 2-8 2-9
Direct Framer Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 T1 Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 E1 Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Hardware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
3.0
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 3.2 0x00-0x3F--Per-Channel Control Registers (per_chan_ctrl). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 0x40--Mode Control Register (mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
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BT8110/8110B
High-Capacity ADPCM Processor
4.0
Electrical and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Microprocessor Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 4.1.2 4.2 4.3 4.4 BT8110 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 ROM Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Appendix A. Hardware Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1.1 A.1.2 A.1.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Functional Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
Appendix B. T1 Speech Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1.1 B.1.2 B.1.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Microprocessor Interface And Per-Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . B-5
Appendix C. E1 Speech Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.1.1 C.1.2 C.1.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 Microprocessor Interface and Per-Channel Configuration. . . . . . . . . . . . . . . . . . . . . . . . C-5
Appendix D. T1 ADPCM Transcoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.1 D.1.2 D.1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 ADPCM Transcoder System Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4
Appendix E. E1 ADPCM Transcoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1
E.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E.1.1 E.1.2 E.1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3 ADPCM Transcoder System Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
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100060C
BT8110/8110B
High-Capacity ADPCM Processor
List of Figures
List of Figures
Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 4-1. Figure 4-2. Figure 4-3. Figure A-1. Figure A-2. Figure A-3. Figure A-4. Figure B-1. Figure B-2. Figure C-1. Figure C-2. Figure D-1. Figure D-2. Figure E-1. Figure E-2. BT8110 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 BT8110 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 BT8110B Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 BT8110B Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 BT8110 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 BT8110B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Input and Output Timing for 24- or 32-Channel Full-Duplex Interleaved Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Input and Output Timing for 48- or 64-Channel Half-Duplex Encoder-Only Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Input and Output Timing for 48- or 64-Channel Half-Duplex Decoder-Only Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Hardware Control Interleaved Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Hardware Control Encoder-Only Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Hardware Control Decoder-Only Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Input and Output Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 68-Pin Plastic Leaded Chip Carrier (J-Bend) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 48- or 64-Channel Configuration of the BT8110/8110B . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 48- or 64-Channel Full-Duplex Interleaved Mode Functional Timing . . . . . . . . . . . . . . . . . . A-3 96- or 128-Channel Half-Duplex Encoder-Only Functional Timing. . . . . . . . . . . . . . . . . . . . A-4 96- or 128-Channel Half-Duplex Decoder-Only Functional Timing . . . . . . . . . . . . . . . . . . . A-5 T1 Speech Compression Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 T1 Speech Compression Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 E1 Speech Compression Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 E1 Speech Compression Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 Single-Board Transcoder Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 Single-Board Transcoder Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3 Single-Board Transcoder Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2 Single-Board Transcoder Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
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List of Figures
BT8110/8110B
High-Capacity ADPCM Processor
vi
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
List of Tables
List of Tables
Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table A-1. Table B-1. Table B-2. Table B-3. Table C-1. Table C-2. Table C-3. Table D-1. Table E-1. ADPCM Operational Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 BT8110 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 BT8110B Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 BT8110/8110B Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Parallel Signal Input Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Parallel Signal Output Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 BT8110/8110B Connection for Hardware Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 BT8110 or BT8110B with External Lookup Table ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 BT8110B Internal Lookup Table ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Interleaved Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Encoder/Decoder-Only Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 BT8110/8110B Hardware Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Input and Output Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 System Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 BT8110/8110B Microprocessor Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Microcontroller Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 BT8110/8110B Processor Per-Channel Control Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 BT8110/8110B Microprocessor Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 BT8110/8110B Microprocessor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 BT8110/B Per-Channel Control Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 ADPCM Transcoder System Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4 ADPCM Transcoder System Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
100060C
Conexant
vii
List of Tables
BT8110/8110B
High-Capacity ADPCM Processor
viii
Conexant
100060C
1
1.0 Product Description
The Adaptive Differential Pulse Code Modulation (ADPCM) algorithm is a transcoding operation which consists of encoding 64 kbit/s Pulse Code Modulation (PCM) to 16, 24, 32, or 40 kbit/s ADPCM and decoding from ADPCM to 64 kbit/s PCM. The multichannel processor provides transcoding for both A-law and -law PCM codes. The PCM coding rate is selectable on a channel-by-channel basis. The BT8110/8110B has a maximum capacity of 64 channels of ADPCM operations. It can be configured to provide 24 or 32 full-duplex channels providing both encoding and decoding. It can also be configured to provide 48 or 64 half-duplex channels providing either encoding or decoding. The BT8110/8110B consists of a VLSI CMOS integrated circuit and a ROM.
NOTE:
In the BT8110, the ROM is external. Additionally, for the BT8110, a 64 K ROM will provide six different ADPCM codes, while a 128 K ROM will provide 14 different ADPCM codes. (See Table 3-1.). The BT8110B has an internal ROM or can be used with the external ROM. The BT8110B's internal ROM contains 14 different ADPCM codes (see Table 3-2),
Two BT8110/8110Bs and a single ROM can be configured to provide 48 or 64 full-duplex channels for operation in transcoding applications. There are two control modes for the BT8110/8110B: Hardware and Microprocessor. The hardware mode provides for input of code selection, transparency selection, algorithm reset, and PCM coding law on a per-channel basis. The microprocessor mode is provided via an integral interface to a microprocessor consisting of a microprocessor, program and data memory, and desired status indicators.
100060C
Conexant
1-1
1.0 Product Description
1.1 Channel Capacity and Configuration Modes
BT8110/8110B High-Capacity ADPCM Processor
1.1 Channel Capacity and Configuration Modes
There are four configurations for the operational mode of the BT8110/8110B (see Table 1-1). These configurations are established by setting the three mode control bits ([MODE[2:0]) and the enable framer bit [EN_FRMR] in the Mode Control Register [mode; 0x40], in the microprocessor mode or on signal pins in the hardware mode (AD[2:0] and CTRL[0]). Table 1-1 summarizes the configurations and the input code applied to each.
Table 1-1. ADPCM Operational Modes CTRL [1]
x x x 0
NOTE(S):
(1)
CTRL [0]
0 0 0 1
Mode Control
100 101 110 100
Function
Encoder/Decoder Interleaved(1) Encoder Only Decoder Only Direct Framer Interface
Clock Rate (MHz)
6.144 6.144 6.144 12.352
Channel Capacity
24 Full-duplex 48 Half-duplex 48 Half-duplex 24 Full-duplex
Clock Rate (MHz)
8.192 8.192 8.192 8.192
Channel Capacity
32 Full-duplex 64 Half-duplex 64 Half-duplex 32 Full-duplex
Interleaved operation means that the BT8110/8110B alternates between encoder and decoder operation on consecutive inputs. This requires that the inputs and outputs be interleaved (PCM/ADPCM/PCM, etc.) as well. 2. CTRL[1] and CTRL[0] are available only in the BT8110B.
In T1 and E1 direct framer interface modes the BT8110/8110B can connect directly to a T1 or E1 framer providing 24 or 32 full-duplex channels of encoding. These configurations are described in detail in Appendix B and C.
1.1.1 Signal Inputs and Outputs
The BT8110/8110B provides both parallel and serial inputs and outputs. The 8-bit parallel inputs are selected by setting the input PSIGEN high. The serial input is a multiplexed encoder/decoder input to provide interleaved signals. The transfer rate of the serial input and output is one-half the input clock rate (CLOCK). The serial output is also multiplexed in interleaved encoder/decoder operation. ADPCM inputs and outputs appear on the most significant bits. The serial signal input and output words are 8 bits, with the most significant bit (sign bit for PCM) appearing first. When transparent operation is selected for a given channel for either an encoder or a decoder, all 8 bits are transferred without modification from the input to both the serial and parallel outputs.
NOTE:
The exception is with the BT8110 when the parallel interface is selected in the direct T1/E1 framer interface mode; then the decoder path PSIG[0] must held at a logic low level.
1-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
1.0 Product Description
1.1 Channel Capacity and Configuration Modes
1.1.2 Embedded Coding
The BT8110/8110B has the capability to provide embedded coding according to ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. This coding technique allows the encoding to be performed with 5 bits of encoding information, and the decoding to be done with anywhere from 2 to 5 input bits. The coding algorithm is defined so that although the coding distortion increases as the number of bits at the decoder decreases, the encoder and the decoder will remain synchronized. The BT8110/8110B is designed so that embedded coding is enabled by the ROM code selected. Along with four different standard (non-embedded) ADPCM codes, two embedded codes can be provided with a 64 K ROM and up to six different embedded codes, with eight different standard (non-embedded) codes, can be provided with a 128 K ROM. The encoder always provides the maximum number of bits (up to 5) defined by the code selected. The decoder requires up to 5 ADPCM bits and a 2-bit encoded input that indicates how many bits are present at the decoder input. This input signal is applied to bits 1 and 2 of the parallel input bus. If embedded coding is not in use, bits 1 and 2 should be connected to ground.
1.1.3 Control Mode
Each channel has four sets of per-channel control inputs. These are for selecting the PCM coding law (A-law or -law), selecting transparent operation, selecting the RESET function of the ADPCM coding algorithm, and selecting which of 14 codes (six codes for a 64 K ROM) is used for encoding or decoding. The microprocessor mode is selected by setting input MICREN high. The microprocessor can address 65 different registers. There is a control register for each of the encoder and decoder channel operations and a mode control register that sets the operating mode of the BT8110/8110B.
100060C
Conexant
1-3
1.0 Product Description
1.2 Pin Descriptions
BT8110/8110B High-Capacity ADPCM Processor
1.2 Pin Descriptions
The BT8110 and BT8110B are packaged as 68-pin Plastic Leaded Chip Carriers (PLCCs). Figures 1-1 and 1-2 illustrate the pinouts for the BT8110 and BT8110B, respectively. Pin assignments are listed in numerical order in Table 1-2 for BT8110, and in Table 1-3 for BT8110B. Figures 1-2 and 1-4 show the functionally partitioned logic diagrams for BT8110 and BT8110B. Pin descriptions, names, and I/O assignments are detailed in Table 1-2.
Figure 1-1. BT8110 Pinout Diagram
GND AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT VCC GND AD[3] RESET SYNC CS MICREN AD[4] AD[5] VCC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
VCC PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] WR* PSIG[3] GND VCC PSIG[2] PSIG[1] PSIG[0] GND A[0] A[1] A[2]
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
BT8110 ADPCM Processor
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
A[3] A[4] A[5] D[0] D[1] D[2] D[3] VCC GND D[4] D[5] D[6] D[7] A[6] A[7] A[8] GND
GND AD[6] ALE PCM_STB ADPCM_STB Y TDP SE GND VCC A[13] AD[12] VCC GND AD[11] AD[10] A[9]
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
100060_002
1-4
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Table 1-2. BT8110 Pin Descriptions Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
1.0 Product Description
1.2 Pin Descriptions
Pin Label
GND PSIG[3] WR* PSIG[4] PSIG[5] PSIG[6] PSIG[7] (MSB) PSIGEN VCC GND AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT VCC GND AD[3] RESET SYNC CS MICREN AD[4] AD[5] VCC GND AD[6] ALE PCM_STB ADPCM_STB Y TDP SE
I/O
I I I I I I I I I I I I I I I O I I I I I I I I I I I I I O O O O O
Pin
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Pin Label
GND VCC A[13] A[12] VCC GND A[11] A[10] A[9] GND A[8] A[7] A[6] D[7] D[6] D[5] D[4] GND VCC D[3] D[2] D[1] D[0] A[5] A[4] A[3] A[2] A[1] A[0] GND PSIG[0] PSIG[1] PSIG[2] VCC
I/O
I I O O I I O O O I O O O I I I I I I I I I I 0 O O O O O I I I I I
100060C
Conexant
1-5
1.0 Product Description
1.2 Pin Descriptions
BT8110/8110B High-Capacity ADPCM Processor
Figure 1-2. BT8110 Logic Diagram
Clock In Sync In Serial Input Reset
I I I I
15 21 14 20 8 7 6 5 4 2 67 66 65 23 29 22 3 28 25 24 19 13 12 11 48 49 50 51 54 55 56 57
Clock and CLOCK Serial SYNC SERIAL_IN Interface RESET PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0] MICREN ALE CS WR* AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
ADPCM_STB PCM_STB SERIAL_OUT
31 30 16
O ADPCM Strobe O PCM Strobe O Serial Output
Parallel Signal Enable I (MSB) Parallel Signal In 7 Parallel Signal In 6 Parallel Signal In 5 Parallel Signal In 4 Parallel Signal In 3 Parallel Signal In 2 Parallel Signal In 1 Parallel Signal In 0 Microcontroller Enable Address Latch Enable Chip Select Write* P Address/Data 6 P Address/Data 5 P Address/Data 4 P Address/Data 3 P Address/Data 2 P Address/Data 1 P Address/Data 0 ROM Data 7 ROM Data 6 ROM Data 5 ROM Data 4 ROM Data 3 ROM Data 2 ROM Data 1 ROM Data 0 I I I I I I I I I I I I I I I I I I I I I I I I I I I
Parallel Input Interface
Microprocessor Interface A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] SE TDP Y 37 38 41 42 43 45 46 47 58 59 60 61 62 63 O O O O O O O O O O O O O O ROM Address 13 ROM Address 12 ROM Address 11 ROM Address 10 ROM Address 9 ROM Address 8 ROM Address 7 ROM Address 6 ROM Address 5 ROM Address 4 ROM Address 3 ROM Address 2 ROM Address 1 ROM Address 0
ROM Interface
Test Interface
34 33 32
O SE Parameter O TDP Parameter O Y Parameter
I = Input, O = Output
100060_003
1-6
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Figure 1-3. BT8110B Pinout Diagram
1.0 Product Description
1.2 Pin Descriptions
GND AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT VCC GND AD[3] RESET SYNC CS MICREN AD[4] AD[5] VCC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
VCC PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] WR* PSIG[3] GND VCC PSIG[2] PSIG[1] PSIG[0] GND A[0] A[1] A[2]
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
BT8110B ADPCM Processor
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
A[3] A[4] A[5] D[0] D[1] D[2] D[3] VCC GND D[4] D[5] D[6] D[7] A[6] A[7] A[8] GND
GND AD[6] ALE PCM_STB ADPCM_STB Y TDP SE GND VCC A[13] A[12] CTRL[1] CTRL[0] A[11] A[10] A[9]
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
100060_004
100060C
Conexant
1-7
1.0 Product Description
1.2 Pin Descriptions
BT8110/8110B High-Capacity ADPCM Processor
Table 1-3. BT8110B Pin Descriptions Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Pin Label
GND PSIG[3] WR* PSIG[4] PSIG[5] PSIG[6] PSIG[7] (MSB) PSIGEN VCC GND AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT VCC GND AD[3] RESET SYNC CS MICREN AD[4] AD[5] VCC GND AD[6] ALE PCM_STB ADPCM_STB Y TDP SE
I/O
I I I I I I I I I I I I I I I O I I I I I I I I I I I I I O O O O O
Pin
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Pin Label
GND VCC A[13] A[12] CTRL[1] CTRL[0] A[11] A[10] A[9] GND A[8] A[7] A[6] D[7] D[6] D[5] D[4] GND VCC D[3] D[2] D[1] D[0] A[5] A[4] A[3] A[2] A[1] A[0] GND PSIG[0] PSIG[1] PSIG[2] VCC
I/O
I I O O I I O O O I O I/O I/O I I I I I I I I I I I/0 I/O I/O I/O I/O I/O I I I I I
1-8
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Figure 1-4. BT8110B Logic Diagram
1.0 Product Description
1.2 Pin Descriptions
Clock In Sync In Serial Input Reset
I I I I
15 21 14 20 8 7 6 5 4 2 67 66 65
Clock and CLOCK Serial SYNC SERIAL_IN Interface RESET PSIGEN PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0]
ADPCM_STB PCM_STB SERIAL_OUT
31 30 16
O ADPCM Strobe O PCM Strobe O Serial Output
Parallel Signal Enable I (MSB) Parallel Signal In 7 Parallel Signal In 6 Parallel Signal In 5 Parallel Signal In 4 Parallel Signal In 3 Parallel Signal In 2 Parallel Signal In 1 Parallel Signal In 0 I I I I I I I I
Parallel Interface (ROM Interface)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
48 49 50 51 54 55 56 57
I/O I/O I/O I/O I/O I/O I/O I/O
ROM Data In/PData Out ROM Data In/PData Out ROM Data In/PData Out ROM Data In/PData Out ROM Data In/PData Out ROM Data In/PData Out ROM Data In/PData Out ROM Data In/PData Out
ROM Interface
A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
37 38 41 42 43 45 46 47 58 59 60 61 62 63
O ROM Address 13 O ROM Address 12 O ROM Address 11 O ROM Address 10 O ROM Address 9 O ROM Address 8 I/O ROM Address 7 I/O ROM Address 6 I/O ROM Address 5 I/O ROM Address 4 I/O ROM Address 3 I/O ROM Address 2 I/O ROM Address 1 I/O ROM Address 0
Microcontroller Enable Address Latch Enable Chip Select Write* P Address/Data 6 P Address/Data 5 P Address/Data 4 P Address/Data 3 P Address/Data 2 P Address/Data 1 P Address/Data 0 Control Inputs Control Inputs
I I I I I I I I I I I I I
23 29 22 3 28 25 24 19 13 12 11 39 40
MICREN ALE CS WR* AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] CTRL[1] CTRL[0]
Microprocessor and Hardware Control Interface
Test Interface
SE TDP Y
34 33 32
O SE Parameter O TDP Parameter O Y Parameter
I = Input, O = Output
100060_005
100060C
Conexant
1-9
1.0 Product Description
1.2 Pin Descriptions
BT8110/8110B High-Capacity ADPCM Processor
Table 1-4. BT8110/8110B Hardware Signal Definitions (1 of 2) Pin Label
CLOCK
Signal Name
Clock
I/O
I
Definition
The system clock provided to the BT8110/8110B. Maximum clock frequency is 16.5 MHz, and it must have minimum high and low periods of 27 ns (duty cycle of 45% to 55% at 16.5 MHz, or 22% to 78% at 8.192 MHz). Provides input and output synchronization. Selects the algorithm reset function per ANSI T1.303-1989 and ITU-T G.726. Active when the parallel ADPCM inputs and outputs are enabled in interleaved mode, and is active for both PCM inputs and ADPCM outputs in encoder mode. This pin is disabled in decoder mode. Active when the parallel PCM inputs and outputs are enabled in interleaved mode, and is active for both ADPCM inputs and PCM outputs in decoder mode. This pin is disabled in encoder mode. This pin has multiplexed PCM and ADPCM signals in interleaved mode; PCM signals for encoder mode, and ADPCM signals for decoder mode. This pin has multiplexed PCM and ADPCM signals in interleaved mode; ADPCM signals for encoder mode, and PCM signals for decoder mode. A control signal that enables parallel inputs. Does not affect parallel outputs (D[7:0]), which are always available. On the BT8110B, this signal has extra functionality (see note in Section 2.2.1.1). The parallel input data bus. The most significant bit (sign bit for PCM, I1 for ADPCM) appears on PSIG[7]. This input bus is also used to indicate ADPCM word length when embedded decoding is performed. When serial inputs are used, these inputs should be left unconnected (internal pull-down resistors included) except as required for embedded decoding. On the BT8110, these signals are inputs, accepting data from the external lookup table ROM. The data on these pins also provides parallel PCM and ADPCM output functionality for the BT8110. On the BT8110B, these signals are outputs when internal ROM is used. D[7] is the most significant bit of the PCM and ADPCM data. Active high input that selects per-channel control via a microprocessor interface. Active high input that enables write operations to the BT8110/8110B. In hardware mode this pin enables transparent operation. Active low input that performs the write operation to the BT8110/8110B. In hardware mode this pin enables A-law PCM coding (low for -law). ALE is a microprocessor-generated signal that causes the BT8110/8110B to latch in the address on the address/data bus. ALE is active high with the address being latched on the falling edge of the signal. In hardware mode this pin becomes an optional code input. Microprocessor 7-bit address and data bus.
SYNC Clock I and Serial Interface RESET(1) ADPCM_STB
Synchronization Reset ADPCM Strobe
I I O
PCM_STB
PCM Strobe
O
SERIAL_IN
Serial Data Input
I
SERIAL_OUT
Serial Data Output
O
PSIGEN
Parallel Signal Enable
I
PSIG[7:0] Parallel Interface
Parallel Signal Input
I
D[7:0]
Parallel Signal Output/ ROM Data Input
I/O
MICREN(1) CS(1) Microprocessor Interface
Microprocessor Enable Chip Select
I I
WR*(1)
Write*
I
ALE(1)
P Address Latch Enable.
I
AD[6:0]
P Address/Data Bus
I
1-10
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Table 1-4. BT8110/8110B Hardware Signal Definitions (2 of 2) Pin Label
A[13:0]
1.0 Product Description
1.2 Pin Descriptions
Signal Name
ROM Address Bus
I/O
I/O
Definition
On the BT8110, these signals are ouputs driving the address lines on the external lookup table ROM. On the BT8110B, A[7:0] are inputs when internal lookup table ROM is used. A[13:8] must be left open when using the BT8110B with internal lookup table ROM enabled. A[7:0] may be left open or held low for normal operation when using BT8110B with internal lookup table ROM enabled. When using the BT8110B with internal lookup table ROM enabled, A[0] and A[3] have the following functions: * A[0] Disable G.726 TR predictor reset. This function forces the output TD of block TONE to a value of 0. * A[3] Disable even-bit inversion in A-law. This function disables even-bit inversion per G.711. Signal A[0] will be sampled at the same input times as the code select inputs, and so "disable predict or reset" can be controlled on a channel-by-channel bases. A[3] is not timed and so it affects every channel. * A[2:0], A[5:4] are used to allow the BT8110B to be compatible with pre-BT8110 designs. * A[7:6] are factory test pins on the BT8110B that must always be open or held at logic low level. On the BT8110B two new control inputs are provided in place of Vcc and GND. CTRL[1] (pin 39) is Vcc in the BT8110, and CTRL[0] is GND in BT8110. The modes that these new control inputs implement are:
ROM Interface CTRL[1,0]
Control Inputs
I
CTRL[1]
low low
CTRL[0]
low high
Mode
Internal ROM only, interleaved, encode only & decode only modes Internal ROM only, direct framer interface. This option provides a hardware-mode direct framer interface. BT8110-compatible mode, external ROM required Not used (production test only)
high high
low high
In BT8110-compatible mode, existing ROMS will work. Supply Voltage VCC GND Supply Ground I I Seven pins are provided for supply voltage on the BT8110. Six pins are provided on the BT8110B. Nine pins are provided for ground on the BT8110. Eight pins are provided on the BT8110B.
SE Test Signals TDP Y
SE Parameter TDP Parameter Y Parameter
O O O
The serial output pin for the SE parameter. Used only for factory test purposes and should be left unconnected. The serial output pin for the TDP parameter. Used only for factory test purposes and should be left unconnected. The serial output pin for the Y parameter. Used only for factory test purposes and should be left unconnected.
NOTE(S):
(1)
All inputs are active high except WR* which adapts to the type of microprocessor being used. See Section 2.1.2.
100060C
Conexant
1-11
1.0 Product Description
1.2 Pin Descriptions
BT8110/8110B High-Capacity ADPCM Processor
1-12
Conexant
100060C
2
2.0 Functional Description
2.1 Overview
Figure 2-1 and Figure 2-2 illustrate block diagrams for BT8110 and BT8110B, respectively. The quantizer and reconstruction tables are stored in the external (BT8110) or internal (BT8110B) ROM that holds the fixed parameter values and lookup tables specified in the ADPCM algorithms. Both the encoder and decoder paths through the ADPCM processor provide the conversion of a 64-kbps -law or A-law PCM channel to and from a 16-, 24-, 32-, or 40-kbit/s ADPCM channel. The logic is arranged in a serial architecture to take full advantage of time sharing of common circuitry. In the encoder path, prior to the conversion of the PCM input to uniform PCM, a difference signal is obtained by subtracting an estimate of the input signal from the input signal itself. An adaptive 3-, 7-, 15-, or 31-level quantizer (or 4-, 8-, or 16-level for embedded codes) is used to assign two, three, four, or five binary digits, respectively, to the value of the difference signal for transmission. An inverse quantizer produces a quantized difference signal from the corresponding binary digits. The signal estimate is added to this quantized difference signal to produce the reconstructed version of the input signal. Both the reconstructed signal and the quantized difference signal are operated upon by an adaptive predictor that produces the estimate of the input signal, thereby completing the feedback loop. The decoder path includes a structure identical to the feedback portion of the encoder, together with a uniform PCM to -law or A-law conversion and synchronous coding adjustment. The synchronous coding adjustment prevents cumulative distortion occurring on synchronous tandem codings (ADPCM-PCM-ADPCM... digital connections) under certain conditions. The synchronous coding adjustment is achieved by adjusting the PCM output codes in a manner that eliminates quantizing distortion in the next ADPCM encoding stage.
100060C
Conexant
2-1
2.0 Functional Description
2.1 Overview
BT8110/8110B High-Capacity ADPCM Processor
Figure 2-1. BT8110 Block Diagram
SYNC SERIAL_IN SERIAL_OUT CLOCK PSIG[7:0] Parallel Processor Quantizer Signal Memory Serial Processor Quantizer Adjustment Memory
ALE, CS, MICREN AD[6:0]
Microprocessor Interface
Predictor Weight Memory
Parallel Signal Output D[7:0] A[13:0] Reconstruction and Quantizer Table Memory ADPCM_STB PCM_STB
Memory Control
100060_006
Figure 2-2. BT8110B Block Diagram
SYNC SERIAL_IN SERIAL_OUT CLOCK PSIG[7:0] Parallel Processor Quantizer Signal Memory Serial Processor Quantizer Adjustment Memory
ALE, CS, MICREN AD[6:0]
Microprocessor Interface
Predictor Weight Memory
Reconstruction and Quantizer Table Memory
D[7:0]
Parallel Signal Output
Memory Control
ADPCM_STB PCM_STB
100060_007
2-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.1 Overview
2.1.1 Clocking and Synchronization
Each operating mode of the BT8110/8110B requires clock and synchronization inputs to allow proper operation. If the microprocessor mode is used, then the synchronization signal frequency can be any submultiple of a PCM frame (8 kHz). If the hardware mode is used, then the synchronization frequency can be any submultiple of 1/32 of the clock frequency; in this case the synchronization signal is used to identify consecutive inputs and outputs. The CLOCK signal must operate at a frequency of 8.192 MHz to obtain the 8 kHz frame rate for PCM signals. This clock can be gapped and may have a peak rate of 16.5 MHz (maximum rate of 16.384 MHz is used in the E1 transcoder application). The SYNC signal must operate at a submultiple of the 8 kHz frame rate. The SYNC signal is active on the falling edge; the rising edge can occur anywhere in the frame. (In direct framer interface mode, the SYNC signal is active on the rising edge.) The SYNC signal synchronizes internal modulo-32 counters and an internal word counter. Its falling edge synchronizes the counters, and this can occur at any submultiple of 8 kHz. ADPCM_STB and PCM_STB are output timing signals that can be used to enable three-state inputs to the parallel input bus and to clock the parallel output bus signals. They are each low for two clock cycles. The rising edge of each signal can be used to clock the parallel output data into an octal register.
2.1.2 Microprocessor Interface
An integral control interface to an Intel 8051-family microprocessor, Motorola 68HC11-family, or equivalent is provided. This microprocessor interface allows the operation mode and the per-channel configuration of the BT8110/8110B to be selected directly from a software-based system. The use of this interface is optional; it is enabled by setting the MICREN control input high. When MICREN is set high, all mode and per-channel configuration is done through the microprocessor. The microprocessor being used should be connected as shown in Table 2-1. The microprocessor interface to the BT8110/8110B consists of 11 pins: P enable (MICREN) address latch enable (ALE), write enable (WR*), chip select (CS), and seven multiplexed address/data bits (AD[6:0]). These signals are connected as shown in Table 2-1. The microprocessor interface is designed to allow the direct connection of an Intel 8051-family or Motorola 68HC11 microprocessor. The chip select input can be taken from one of the address inputs or from an address decoding circuit to locate the BT8110/8110B within any desired memory address range. The chip select input to the BT8110/8110B allows the control of multiple circuits from a single microprocessor. The microprocessor interface is write-only. Data read from the address space of the BT8110/8110B will be invalid.
100060C
Conexant
2-3
2.0 Functional Description
2.1 Overview
BT8110/8110B High-Capacity ADPCM Processor
Table 2-1. Signal Connections BT8110/8110B Pin
MICREN ALE WR* CS AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
P Enable Address Latch Enable Write Enable Chip Select Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
Intel 8051
VCC ALE WR* A[n] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Motorola 68HC11
VCC AS E A[n] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
The interface for the Intel 8051 or Motorola 68HC11 microprocessors comprises the latch enable signal, the write enable (8051) or enable signal (68HC11), the chip select signal (one pin from port P2 of the 8051) and the seven low bits of the 8-bit address/data bus (port P0 of the 8051). For the 68HC11 microprocessor, the enable signal E is connected to the write enable pin. The setup and hold times required for the latch enable and write enable signals are 10 ns. Other (much faster) processors can be used as long as the multiplexed address/data bus feature of the 8051 is supported. Detailed timing requirements for the microprocessor interface are given in Section 4.1.
2.1.3 Address Map
The address map for the controller is given in the Register Summary, Table 3-3 and Table 3-4, where both interleaved and encoder/decoder operations are shown. The internal control registers for the 32 encoders and the 32 decoders for interleaved operation are located at addresses 0x00-0x3F. A write to address 0x40 will load the Mode Control Register [mode; 0x40].
2-4
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.2 Modes of Operation
2.2 Modes of Operation
This section details the functional timing of the clock, synchronization, and signal interfaces. The data and control interfaces include the clock and synchronization inputs, the PCM and ADPCM inputs and outputs, and the control inputs to select algorithm reset, transparent operation, PCM code type, and the selected coding algorithm when the microprocessor interface is not selected. The 24- or 32-channel full-duplex interleaved encoder and decoder operation is presented first, followed by 48- or 64-channel encoder-only operation, and 48- or 64-channel decoder-only operation.
2.2.1 24- or 32-Channel Full-Duplex Interleaved Operation
Figure 2-3 illustrates the operation of the BT8110/8110B in 24- or 32-channel full-duplex interleaved mode with microprocessor control. The channel numbers in parentheses are for the 24-channel full-duplex mode. In this diagram, inputs are shown changing on negative edges of the input clock, and outputs are shown changing on positive edges. This is the recommended method for operating the BT8110/8110B to avoid any timing problems. Detailed timing parameters are given in Chapter 4.0. To operate the BT8110/8110B in the 24- or 32-channel full-duplex interleaved mode, the Mode Control Register located at address 0x40 should be set to a value of 0x0C for 32 channels, 0x04 for 24 channels. In many 24-channel configurations, a gapped clock will be used to account for the frame bit of the T1 signal; this operates correctly as long as there are exactly 32 clock cycles per channel processed.
100060C
Conexant
2-5
2.0 Functional Description
2.2 Modes of Operation
BT8110/8110B High-Capacity ADPCM Processor
Figure 2-3. Input and Output Timing for 24- or 32-Channel Full-Duplex Interleaved Operation (Microprocessor Control)
Ref. Cycle 8.192 (6.144) MHz Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-31 (23) RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-30 (22) D[7:0] Int (1) ADPCM-30 (22) PCM-29 (21) ADPCM-31 (23) PCM-29 (21) ADPCM-31 (23)
5 6 7 8 I1 I2 I3 I4 I5 S 2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
I1
I2
I3
I4
I5
S
2
3
4
5
6
7
8
I1
I2
I3
I4
I5
ADPCM-31 (23)
PCM-0 PCM-0 ADPCM-0
3 4 5 6
ADPCM-0 ADPCM-0
7
8
I1
I2
ADPCM-30 (22)
PCM-29 (21)
NOTE(S): (1) BT8110B only.
100060_008
2.2.1.1 Signal Inputs and Outputs
Either serial or parallel signal inputs can be used in all modes. When the PSIGEN input is tied high, the parallel signal inputs for both PCM and ADPCM are enabled. The SERIAL_IN signal contains the serial PCM encoder input, sign bit first, and the serial ADPCM input. (The ADPCM values are preceded by I with I1 being the most significant bit.) The input is applied at a rate of 4.096 Mbit/s (3.072 Mbit/s for 24-channel). The timing is arranged as shown so that the middle of bit 3 of the ADPCM is coincident with falling edges of SYNC. For codes of less than 5 bits, the unused serial input ADPCM bits must be set to zero. The PSIG[7:0] signal is used for the signal input when PSIGEN is high. It is also used for the ADPCM word length indication when embedded decoding is performed. Table 2-2 is the arrangement of the input bits on the bus.
NOTE:
On the BT8110B only, a latch has been added to the parallel input signal enable, PSIGEN. This signal now has the same input timing as the parallel input itself. This allows different inputs for the encoder and decoder, respectively, in interleaved mode, and using the serial input for idle code insertion under control of PSIGEN when the normal input is parallel mode, or vice versa.
2-6
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.2 Modes of Operation
Bits e1 and e0 of the decoder input are used only for embedded coding operation where they specify the number of bits in the applied decoder input. Unused decoder input bits must be set to 0.
Table 2-2. Parallel Signal Input Bus Input Bus
PSIG[7] PSIG[6] PSIG[5] PSIG[4] PSIG[3] PSIG[2] PSIG[1] PSIG[0]
Encoder In
Sign Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Decoder In
I1 I2 I3 I4 I5 e1 - 0 for 3 or 2 bits, 1 for 5 or 4 bits e0 - 0 for 4 or 2 bits, 1 for 5 or 3 bits 0
If PSIGEN is low, the only PSIG[7:0] bus inputs used are PSIG[2] and PSIG[1]. These are used as inputs for embedded decoding. The other PSIG inputs should be held at a logic low level; these inputs have internal pull-down circuits. Driving these inputs when only serial inputs are enabled will induce test modes in the part that will interfere with proper operation. SERIAL_OUT represents the timing on the serial ADPCM signals as shown in Figure 2-3. The ADPCM output is from the channel whose PCM signal was applied 56 clock cycles previously. The PCM output is from the channel whose ADPCM input was applied 88 clock cycles previously. Unused ADPCM output bits are set to 0. D[7:0] outputs are the 8 output bits of the ROM and are used for the parallel signal outputs at the indicated time. Table 2-3 gives the arrangement of the output bits on the bus.
NOTE:
On BT8110B only, when internal ROM is used, the bidirect outputs D[7:0] will contain the PCM/ADPCM output values, MSB on D[7]. Each output word will be latched simultaneously with the falling edge of the PCM and ADPCM strobe signals. In interleaved mode, the output timing will appear as shown by signal D[7:0] Int in Figure 2-3.
The delay of the parallel outputs can be observed in Figure 2-3. When parallel inputs are used, the ADPCM output for encoder operations is available 48 clock cycles after the input is applied. The PCM output of decoder operations is available 80 clock cycles after the input is applied. When the channel control is set for transparent operation, the 8-bit output field is exactly the same as the 8-bit input field for either parallel or serial inputs. The delay is kept the same as for coding operations.
100060C
Conexant
2-7
2.0 Functional Description
2.2 Modes of Operation
BT8110/8110B High-Capacity ADPCM Processor
Table 2-3. Parallel Signal Output Bus Output Bus Bit
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Decoder Out
Sign Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
Encoder Out
I1 I2 I3 I4 I5 0 0 0
2.2.1.2 Reset Control
The RESET signal pin can be used to reset the algorithm according to ANSI T1.303-1989 and ITU-T G.726 when microprocessor operation mode is used; the reset control bit [EN_RST; per_chan_ctrl.5] can also set this function. The real-time algorithm reset function is useful in Digital Circuit Multiplication Equipment (DCME), packet-voice, and speech storage applications. The RESET input is active during the time interval shown in Figure 2-3.
2.2.2 48- or 64-Channel Encoder-Only Operation
Figure 2-4 shows the functional timing for 48- or 64-channel half-duplex encoder-only operation. The channel numbers in parentheses are for the 48-channel encoder-only mode. The timing is generally the same as for interleaved timing, but the inputs are all PCM for encoding, and the outputs are all ADPCM. In this mode of operation, the ADPCM_STB signal occurs once every 16 clock cycles and the PCM_STB signal is not active. This keeps the ADPCM_STB signal periodic with both the inputs and the outputs when the parallel input interface is used. To operate the BT8110/8110B in the 48- or 64- channel encoder-only mode, the Mode Control Register should be set to a value of 0x0D for 64 channels or 0x05 for 48 channels. In many 48-channel configurations, a gapped clock will be used to account for the frame bit of the T1 signal; this operates correctly as long as there are exactly 32 clock cycles per channel processed. The address table for the microprocessor per-channel controls (encoder/decoder operation only) is given in the Register Summary, Table 3-4.
2-8
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.2 Modes of Operation
Figure 2-4. Input and Output Timing for 48- or 64-Channel Half-Duplex Encoder-Only Operation (Microprocessor Control)
Ref. Cycle 8.192 (6.144) MHz Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] PCM-63 (47) RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-60 (44) D[7:0] Int (1) ADPCM-60 (44) ADPCM-61 (45) ADPCM-62 (46) ADPCM-61 (45) ADPCM-62 (46)
I5 I1 I2 I3 I4 I5 I1 I2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S
2
3
4
5
6
7
8
S
2
3
4
5
6
7
8
S
2
3
4
5
6
PCM-63 (47)
PCM-0 PCM-0 PCM-1
I3 I4 I5
PCM-1 PCM-1
I1
I2
ADPCM-60 (44)
ADPCM-61 (45)
NOTE(S): (1) BT8110B only.
100060_009
2.2.3 48- or 64-Channel Decoder-Only Operation
Figure 2-5 shows the functional timing for 48- or 64-channel decoder-only operation. The channel numbers in parentheses are for the 48-channel mode. Again, the timing is generally the same as for interleaved timing, but the inputs are all ADPCM and the outputs are all PCM. Here, PCM_STB is active every 16 clock cycles, and ADPCM_STB is not active. To operate the BT8110/8110B in the 48- or 64-channel decoder-only, the Mode Control Register should be set to a value of 0x0E for 64 channels or 0x06 for 48 channels. The address table for the microprocessor per-channel controls (encoder/decoder-only operation) is the same as for encoder-only operation and is given in the Register Summary, Table 3-4.
100060C
Conexant
2-9
2.0 Functional Description
2.2 Modes of Operation
BT8110/8110B High-Capacity ADPCM Processor
Figure 2-5. Input and Output Timing for 48- or 64-Channel Half-Duplex Decoder-Only Operation (Microprocessor Control)
Ref. Cycle 8.192 (6.144) MHz Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-63 (47) RESET ADPCM-0 SERIAL_OUT D[7:0] PCM-58 (42) D[7:0] Int (1) PCM-58 (42) PCM-59 (43) PCM-60 (44) PCM-59 (43) PCM-60 (44)
5 6 7 8 S 2 3 4 5 6 7 8 S 2 I1 I2 I3 I4 I5 I1 I2 I3 I4 I5 I1 I2 I3 I4 I5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ADPCM-63 (47)
ADPCM-0 ADPCM-0 ADPCM-1
3 4 5 6
ADPCM-1 ADPCM-1
7
8
S
2
PCM-58 (42)
ADPCM-59 (43)
NOTE(S): (1) BT8110B only.
100060_010
2-10
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.3 Direct Framer Interface Operation
2.3 Direct Framer Interface Operation
The direct framer interface operation modes are intended for voice compression and storage applications such as voice mail, voice message store and forward, or voice response. For more details, see the Speech Compression Interface application notes, Appendix B and C of this specification.
2.3.1 T1 Framer Interface
In this configuration, address 0x40 must be set to a value of 0x14 to properly set the BT8110/8110B mode. The per-channel control registers given in Table 3-3 must be configured for the appropriate code selection, coding type, and transparency. The BT8110 allows only 56 kbit/s data rate in transparent mode. The BT8110B operates at a full 64 kbit/s data rate. The full-rate PCM signals are serial and are connected directly to the SERIAL_IN and SERIAL_OUT pins. In this application, the PSIGEN input must be held low, thus enabling the parallel interface for the ADPCM inputs PSIG[7:0] and outputs D[7:0]. The ADPCM inputs and outputs are timed by the signal ADPCM_STB. The ADPCM input to the BT8110/8110B is applied to the parallel input PSIG[7:3] with the most significant bit at PSIG[7]. The ADPCM output is obtained from the Parallel Signal Output Bus D[7:0] with the most significant bit at D[7]. The BT8110/8110B interfaces to a T1 framer, which is used to transmit and receive a digital line at the 1.544 Mbit/s rate. The slip buffer of the T1 framer frame-synchronizes the receive signal to the transmit signal so that the BT8110/8110B can operate synchronously on both signals. The ADPCM input data must be valid at the positive edge of ADPCM_STB; the ADPCM output data is valid at the positive edge. Due to the processing delay of the BT8110/8110B, there is a five-channel offset between the timing of the ADPCM input and PCM output. The ADPCM output is always 5 bits (for 40 kbit/s coding and for all embedded codes) or less. The ADPCM input includes up to 5 ADPCM input bits and 2 bits to indicate the number of bits in the decoder input when embedded encoding is used. On the BT8110 only, the input to PSIG[0], the least significant bit, must be left open or held at a logic low level (this pin has an internal pull-down resistor). The 6.144 MHz clock is obtained by internally dividing and gapping the 12.352 MHz input clock to the BT8110. The required 12.352 MHz signal source should be phase-locked to incoming PCM data. A complete implementation of a 48-channel T1 speech compression interface utilizing the Conexant Bt8300 Dual T1-Framer and the BT8110/8110B is detailed in Appendix B, T1 Speech Compression Interface.
100060C
Conexant
2-11
2.0 Functional Description
2.3 Direct Framer Interface Operation
BT8110/8110B High-Capacity ADPCM Processor
2.3.2 E1 Framer Interface
In this configuration, address 0x40 must be set to a value of 0x1C to properly set the BT8110/8110B mode. The per-channel control registers given in Table 3-3 must be configured for the appropriate code selection, coding type, and transparency. The BT8110 allows only 56 kbit/s data rate in transparent mode. The BT8110B operates at a full 64 kbit/s data rate. The full-rate PCM signals are serial and are connected directly to the SERIAL_IN and SERIAL_OUT pins. In this application the PSIGEN input must be held low, thus enabling the parallel interface for the ADPCM inputs PSIG[7:0] and outputs D[7:0]. The ADPCM inputs and outputs are timed by the signal ADPCM_STB. The input to each BT8110 is applied to the parallel input PSIG[7:0] with the most significant bit at PSIG[7]. The output is obtained from the ROM data bus D[7:0] with the most significant bit at D[7]. The BT8110/8110B interfaces to the E1 framer which transmits and receives a digital line at the 2.048 Mbit/s primary rate. The slip buffer of the E1 framer frame-synchronizes the receive signal to the transmit signal allowing the BT8110/8110B to operate synchronously on both signals. The ADPCM input data must be valid at the positive edge of ADPCM_STB; the ADPCM output data is valid at the positive edge. Due to the processing delay of the BT8110/8110B, there is a five-channel offset between the timing of the ADPCM input and PCM output. The ADPCM output is always 5 bits (for 40 kbit/s coding and for all embedded codes) or less. The ADPCM input includes up to 5 ADPCM input bits and 2 bits to indicate the number of bits in the decoder input when embedded encoding is used. On the BT8110 only, the input to PSIG[0], the least significant bit, must be left open or held at a logic low level (this pin has an internal pull-down resistor). The required 8.192 MHz clock source should be phased-locked to incoming PCM data. A complete implementation of a 60-channel E1 speech compression interface utilizing the Bt8510 E1 Framer and the BT8110/8110B is detailed in Appendix C, E1 Speech Compression Interface.
2-12
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
2.0 Functional Description
2.4 Hardware Control
2.4 Hardware Control
Some applications require precise timing of the modification of the code selected, transparent operation, or coding law. In these cases, the control signals can be provided by hardware and are updated each time a PCM encoder input or an ADPCM decoder input is applied. Serial or parallel inputs can be used. Table 2-4. defines the functions and inputs of the control pins for hardware control.
Table 2-4. BT8110/8110B Connection for Hardware Mode BT8110/8110B Pin
MICREN ALE WR* CS AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
P Enable Optional Coding Enable A-Law PCM Enable Transparent Mode Bit 0 Mode Bit 1 Mode Bit 2 32-Channel Operation Code Bit 0 Code Bit 1 Embedded Coding
Hardware Mode
GND OPT (CODE[3]) A-LAW TRNSPT MODE[0] MODE[1] MODE[2] CH32 CODE[0] CODE[1] EMB (CODE[2])
Pin #
23 29 3 22 11 12 13 19 24 25 28
NOTE(S): The four CODE[n] pins (24, 25, 28, and 29) address the 14 ROM code locations
when using hardware control mode.
100060C
Conexant
2-13
2.0 Functional Description
2.4 Hardware Control
BT8110/8110B High-Capacity ADPCM Processor
2.4.1 Mode Pins
Mode Control (AD[2:0]) and Enable 32-Channel Operation (AD[3]) control pins are fixed for a given operational configuration and are not subject to timing specifications. Mode and control operation pins are defined in Table 2-5. The enable 32-channel operation input is set high for 32- and 64-channel operation and low for 24- and 48-channel operation.
Table 2-5. Mode Pins AD[2]
1 1 1 1 0 0 0 0 0 0
NOTE(S):
(1)
AD[1]
0 0 1 1 0 1 0 1 1 0
AD[0]
0 1 0 1 1 0 1 1 0 0
Source
Interleaved Encoder Decoder Only used for pre-BT8110 design compatibility. Interleaved Processor #1 48/64(1) Interleaved Processor #2 48/64(1) Encoder Processor #1 48/64(1) Encoder Processor #2 48/64(1) Decoder Processor #1 48/64(1) Decoder Processor #2 48/64(1)
See Appendix A for additional information.
2.4.2 Control Pins
Four pins control the coding (AD[6:4], ALE), one pin selects the PCM coding law (WR*), and one pin selects transparent operation (CS). Figure 2-6 illustrates the functional timing of these inputs. Figure 2-7 and Figure 2-8 detail encoder-only operation and decoder-only operation, respectively. The code select input pins have the same timing requirement as the parallel signal inputs on PSIGEN. The transparent enable and A-law enable controls are applied two clock cycles after the reset input and six clock cycles before the coding input. Detailed timing requirements are provided in Chapter 4.0.
2-14
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Figure 2-6. Hardware Control Interleaved Timing
Ref. Cycle 8.192 (6.144) MHz Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] CODE[1], CODE[0] OPT, EMB RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-30 (22) D[7:0] Int (1) ADPCM-30 (22) PCM-29 (21) PCM-29 (21)
5 6 7 8 I1 I2 I3 I4 I5 S 2
2.0 Functional Description
2.4 Hardware Control
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
I1
I2
I3
I4
I5
S
2
3
4
5
6
7
8
I1
I2
I3
I4
I5
ADPCM-31 (23)
PCM-0
ADPCM-0
ADPCM-31 (23)
PCM-0
ADPCM-0
ADPCM-0
3 4 5 6 7 8 I1 I2
ADPCM-30 (22)
PCM-29 (21) ADPCM-31 (23) ADPCM-31 (23)
NOTE(S): (1) BT8110B only.
100060_011
100060C
Conexant
2-15
2.0 Functional Description
2.4 Hardware Control
BT8110/8110B High-Capacity ADPCM Processor
Figure 2-7. Hardware Control Encoder-Only Timing
Ref. Cycle 8.192 (6.144) MHz Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] CODE[1], CODE[0] OPT, EMB RESET PCM-0 SERIAL_OUT D[7:0] ADPCM-60 (44) D[7:0] Int
(1)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S
2
3
4
5
6
7
8
S
2
3
4
5
6
7
8
S
2
3
4
5
6
PCM-63 (47)
PCM-0
PCM-1
PCM-63 (47)
PCM-0
PCM-1
PCM-1
I4 I5 I1 I2 I3 I4 I5 I1 I2
I5
I1
I2
I3
ADPCM-60 (44)
ADPCM-61 (45) ADPCM-61 (45) ADPCM-61 (45) ADPCM-62 (46) ADPCM-62 (46)
ADPCM-60 (44)
NOTE(S): (1) BT8110B only.
100060_012
2-16
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Figure 2-8. Hardware Control Decoder-Only Timing
2.0 Functional Description
2.4 Hardware Control
Ref. Cycle 8.192 (6.144) MHz Clock SYNC ADPCM_STB PCM_STB 4.096 (3.072) Mbit/s SERIAL_IN PSIG[7:0] CODE[1], CODE[0] OPT, EMB RESET
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
I2
I2
I3
I4
I5
I1
I2
I3
I4
I5
I1
I2
I3
I4
I5
ADPCM-63 (47)
ADPCM-0
ADPCM-1
ADPCM-63 (47)
ADPCM-0
ADPCM-1
ADPCM-0 SERIAL_OUT D[7:0] PCM-58 (42) D[7:0] Int (1) PCM-58 (42) PCM-59 (43)
5 6 7 8 S 2 3 4 5 6 7 8 S 2
ADPCM-1
3 4 5 6 7 8 S 2
PCM-58 (42)
ADPCM-59 (43) PCM-60 (44) PCM-59 (43) PCM-60 (44)
NOTE(S): (1) BT8110B only.
100060_013
100060C
Conexant
2-17
2.0 Functional Description
2.4 Hardware Control
BT8110/8110B High-Capacity ADPCM Processor
2-18
Conexant
100060C
3
3.0 Registers
NOTE:
For a summary of all registers refer to the Register Summary section at the end of this chapter.
3.1 0x00-0x3F--Per-Channel Control Registers (per_chan_ctrl)
Per-channel Control Registers can be used by the microprocessor to set the code selection, transparency, algorithm reset, and PCM coding type on a per-channel basis. This capability allows each channel configuration to be set without having to generate input control signals in hardware for each channel. Per-channel control registers are write-only. Any attempt by the microprocessor to read these registers will result in erroneous data. Four code select bits (CODE[3:0]) select up to 14 different codes from ROM. This allows a single BT8110/8110B to realize all of the ADPCM coding algorithms contained in the ANSI standards and ITU-T recommendations for ADPCM coding. Maximum flexibility can be achieved with a single device for all ADPCM applications. Specific code assignments depend on the coding of the ROM that is a part of the BT8110/8110B set. The standard codes that can be provided are the 32 kbit/s code in ITU-T Recommendation G.726 and ANSI Standard T1.303-1989, the 24 and 40 kbit/s codes given in ANSI Standard T1.303-1989, and all of the embedded codes in ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. Only six of the codes can be embedded codes.
6 EN_ALAW 5 EN_RST 4 EN_TRPT 3 CODE[3] 2 CODE[2] 1 CODE[1] 0 CODE[0]
EN_ALAW
Enable A-Law Coding--Sets the encoder PCM input and decoder PCM output coding law to A-law. If this control is not set, the coding law is -law. Enable Reset--Causes the algorithm reset input to be continuously applied as long as the bit is set. This function is according to ANSI Standard T1.303-1989 and is useful for Digital Circuit Multiplexing Equipment (DCME) functions. Enable Transparent Operation--Uses the BT8110/8110B to transfer the 8-bit input to the output without any modifications for both encoder and decoder channels. The delay of the BT8110/8110B is the same for transparent operation as it is for coded (normal) operation. Code Select--Selects among the 14 codes contained in the ROM lookup table. For the BT8110 this table is provided by Conexant in a 128 K ROM, upon request. Each code block is 1024 bytes and can be reorganized in the ROM by the user, except for blocks 6 and 7 which are reserved.
EN_RST
EN_TRPT
CODE[3:0]
100060C
Conexant
3-1
3.0 Registers
3.1 0x00-0x3F--Per-Channel Control Registers (per_chan_ctrl)
BT8110/8110B
High-Capacity ADPCM Processor
Table 3-1. BT8110 or BT8110B with External Lookup Table ROM CODE[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 32 kbit/s G.726 24 kbit/s G.726 16 kbit/s G.726/G.727 40 kbit/s G.726 Unused Unused Reserved Reserved 32 kbit/s Conexant (data optimized) 24 kbit/s Tellabs 16 kbit/s Alternate (3-level) 16 kbit/s Alternate (4-level) G.727 (5,5)--Embedded Code G.727 (x,4)--Embedded Code G.727 (x,3)--Embedded Code G.727 (x,2)--Embedded Code
ROM Code Table
NOTE(S): See Section 4.1.2, ROM Specification Section.
Table 3-2. BT8110B Internal Lookup Table ROM (1 of 2) CODE[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 32 kbit/s G.726 24 kbit/s G.726 16 kbit/s G.726/G.727 40 kbit/s G.726 32 kbit/s G.721-1984 (16-level) 24 kbit/s Tellabs 16 kbit/s Alternate (4-level) Not available 32 kbit/s Conexant (data optimized) Not available 16 kbit/s Alternate (3-level) 16 kbit/s Alternate (4-level)
Internal ROM Code Table
3-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
3.0 Registers
3.2 0x40--Mode Control Register (mode)
Table 3-2. BT8110B Internal Lookup Table ROM (2 of 2) CODE[3:0]
1100 1101 1110 1111
Internal ROM Code Table
G.727 (5,5)--Embedded Code G.727 (x,4)--Embedded Code G.727 (x,3)--Embedded Code G.727 (x,2)--Embedded Code
3.2 0x40--Mode Control Register (mode)
A write to address 0x40 will address the mode control registers for all 24 or 32 channels. Five bits are used to control the mode of operation of the BT8110/8110B. This register is write-only.
6 RSVD 5 RSVD 4 EN_FRMR 3 EN_32CH 2 MODE[2] 1 MODE[1] 0 MODE[0]
RSVD EN_FRMR EN_32CH
Reserved--Unused; should be set to a logic low. Enable Direct T1/E1 Framer Interface--Set for direct connection to a T1 or E1 framer circuit. Enable 32-Channel Operation--Set for 32-channel full duplex or 64-channel half-duplex operation. If it is not set, 24-channel full-duplex or 48-channel half-duplex operation is obtained. Mode Control--Set to the values required to obtain the desired operating mode configuration as follows:
Bit 2 1 1 1 1 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Source Interleaved Encoder Decoder Not Used
MODE[2:0]
100060C
Conexant
3-3
3.0 Registers
3.2 0x40--Mode Control Register (mode)
BT8110/8110B
High-Capacity ADPCM Processor
3-4
Conexant
100060C
3
100060C
Read/ Write 7
RSVD RSVD RSVD RSVD RSVD RSVD
* * * * * * * * * * * * * * * * * * * *
Register Summary
BT8110/8110B
Table 3-3. Interleaved Operation Bit Number 6
EN_ALAW EN_ALAW EN_ALAW EN_ALAW EN_ALAW EN_ALAW EN_RST EN_TRPT CODE[3] EN_RST EN_TRPT CODE[3] EN_RST EN_TRPT CODE[3] EN_RST EN_TRPT CODE[3] CODE[2] CODE[2] CODE[2] CODE[2]
* * * *
ADDR (hex) 5
EN_RST EN_RST EN_TRPT CODE[3] CODE[2] EN_TRPT CODE[3] CODE[2]
Register Label 4 3 2 1
CODE[1] CODE[1] CODE[1] CODE[1] CODE[1] CODE[1]
* * * *
0
CODE[0] CODE[0] CODE[0] CODE[0] CODE[0] CODE[0]
* * * *
High-Capacity ADPCM Processor
00 W W W W W
* * * *
ENC 0
W
01
DEC 0
02
ENC 1
03
DEC 1
04
ENC 2
05
DEC 2
*
*
*
*
Conexant
W W W W W RSVD RSVD RSVD EN_ALAW EN_RST RSVD RSVD EN_ALAW EN_RST RSVD EN_ALAW EN_RST RSVD EN_ALAW EN_RST EN_TRPT EN_TRPT EN_TRPT EN_TRPT EN_FRMR
*
*
*
*
0x3C
ENC 30
CODE[3] CODE[3] CODE[3] CODE[3] EN_32CH
CODE[2] CODE[2] CODE[2] CODE[2] MODE[2]
CODE[1] CODE[1] CODE[1] CODE[1] MODE[1]
CODE[0] CODE[0] CODE[0] CODE[0] MODE[0]
0x3D
DEC 30
0x3E
ENC 31
0x3F
DEC 31
0x40
MODE
3-5
3-6
Read/ Write 7
RSVD RSVD RSVD
* * * * * * * * * * * * * * * * * *
Table 3-4. Encoder/Decoder-Only Operation Bit Number 6
EN_ALAW EN_ALAW EN_ALAW EN_RST EN_TRPT CODE[3] CODE[2] EN_RST EN_TRPT CODE[3] CODE[2] CODE[1] CODE[1]
* * *
ADDR (hex) 5
EN_RST EN_TRPT CODE[3] CODE[2] CODE[1]
Register Label 4 3 2 1 0
W W W
* * *
00
ENC/DEC 0
CODE[0] CODE[0] CODE[0]
* * *
01
ENC/DEC 1
02
ENC/DEC 2
*
*
*
*
*
*
0x3E W W RSVD RSVD RSVD EN_FRMR EN_32CH RSVD EN_ALAW EN_RST EN_TRPT CODE[3]
ENC/DEC 62
W
RSVD
EN_ALAW
EN_RST
EN_TRPT
CODE[3]
CODE[2] CODE[2] MODE[2]
CODE[1] CODE[1] MODE[1]
CODE[0] CODE[0] MODE[0]
0x3F
ENC/DEC 63
0x40
MODE
Conexant
High-Capacity ADPCM Processor
BT8110/8110B
100060C
4
4.0 Electrical and Mechanical Specifications
4.1 Microprocessor Interface Timing
To enable the microprocessor interface, MICREN must be at a logic high level. The pinouts for the controller interface are connected as given in Table 2-1 for either the 8051 or the 68HC11 controller. Figure 4-1 illustrates the timing requirements for the microprocessor interface inputs. The WR* control is active low (write) for the 8051 and latches data on the rising edge and the E control is active high (write) for the 68HC11. The appropriate input is identified as the write enable signal. The CS input is active high. Address data is latched on the falling edge of ALE and is independent of the CS input. The write cycle time is equal to six system clock cycles, and varies from 360 ns for a 16.384 MHz clock to 960 ns for a 6.144 MHz clock. The write cycle time is measured from the end of one write cycle (rising edge of WR*) to the beginning edge of the next write cycle.
Table 4-1. Microprocessor Interface Timing Parameter
TADWRH TADRDL TWRW TAS TAH TCLCL TDS TDH(1) TWR
NOTE(S):
(1) (2)
Description
Select to Write High Select to Read Low Write Pulse Width Address Setup before ALE Low Address Hold after ALE Low ALE Low to Write/Read Low Write Data Stable before Write High Write Data Hold after Write High Write Cycle Time
Min
25 ns 10 ns 25 ns 7 ns 10 ns 10 ns 25 ns 10 ns 732 ns(2)
Typ
- - - - - - - - -
Max
- - - - - - - - -
The external address/data bus capacitance will increase the data hold time if the bus remains undriven. Time given is for a nominal 8.192 MHz input clock frequency. The minimum time allowed should be six times the input clock period. The write cycle time is measured from the end of one write cycle (rising edge of WR*) to the beginning edge of the next write cycle.
100060C
Conexant
4-1
4.0 Electrical and Mechanical Specifications
4.1 Microprocessor Interface Timing
BT8110/8110B High-Capacity ADPCM Processor
Figure 4-1. Microprocessor Interface Timing
CS TADWRH TADRDL WR* (8051) E (68HC11) TWRW
AD[6:0] TAS ALE
100060_014
TAH TCLCL
TDS
TDH
4.1.1 BT8110 Timing
The BT8110/8110B is a fully static synchronous digital processor. The inputs MICREN, PSIGEN, and hardware mode AD[3:0] are all configuration inputs and fixed for a given operating mode. All other inputs are sampled on positive clock transitions. SERIAL_IN and D[7:0] inputs are sampled every other clock cycle; other inputs are sampled every 16 clock cycles. The setup and hold times for the ROM data are controlled by the internal circuits of the BT8110/8110B to allow operation using a ROM with 0 ns hold time. Tables 4-2 and 4-3 give setup and hold times for all of the inputs and a reference clock cycle relative to the SYNC signal input for a given channel during hardware mode operation. All outputs settle within 30 ns (TPDmax) of the corresponding clock positive transition to less than 0.5 V for logic low outputs and greater than VCC -0.5 V for logic high outputs into a 50 pF load (see Figure 4-2).
4-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
4.0 Electrical and Mechanical Specifications
4.1 Microprocessor Interface Timing
Table 4-2. BT8110/8110B Hardware Mode Timing Signal Name
SYNC SERIAL_IN RESET CS WR* PSIG[7:0] ALE AD[6] AD[5] AD[4]
Functions
Multiframe SYNC Serial PCM/ADPCM Input Enable Algorithm Reset Enable Transparent Operation Enable A-Law PCM Coding Parallel PCM/ADPCM Input Optional Code Input, CODE[3] Optional Code Input, CODE[2] Optional Code Input, CODE[1] Optional Code Input, CODE[0]
Reference Cycle
0 0 9 12 12 18 18 18 18 18
Setup Time (TSU)
0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns
Hold Time (THD)
20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns
Table 4-3. Input and Output Signal Timing Parameter
TSU THD TPD
Description
Input Setup Time Input Hold Time Output Setting Time
Min
0 ns 20 ns -
Typ
- - -
Max
-
30 ns
Figure 4-2. Input and Output Signal Timing
Clock Output Signal Input Clock Input Signal TSU TPD THD
100060_015
100060C
Conexant
4-3
4.0 Electrical and Mechanical Specifications
4.1 Microprocessor Interface Timing
BT8110/8110B High-Capacity ADPCM Processor
4.1.2 ROM Specifications
The ROM used as a part of the BT8110/8110B requires an access time of less than two clock cycles. The worst-case internal propagation delays total 30 ns requiring the ROM access time to be 30 ns less than two clock periods. Recommended access times for the system clock frequencies are shown in Table 4-4.
Table 4-4. System Clock Frequencies Clock Frequency
6.144 MHz 8.192 MHz 12.288 MHz 16.384 MHz
Access Time
250 ns 200 ns 125 ns 90 ns
4-4
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
4.0 Electrical and Mechanical Specifications
4.2 Absolute Maximum Ratings
4.2 Absolute Maximum Ratings
The power consumption is proportional to the internal BT8110/8110B system clock rate as shown in Table 4-5; however, the ROM power is not included. Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the other sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup.
Table 4-5. Absolute Maximum Ratings Parameter
Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Operating Supply Voltage BT8110: Maximum Current @ 8.192 MHz (internal clk) BT8110B: Maximum Current @ 8.192 MHz (internal clk)
Symbol
VDD VIN VOUT TA TSTG VCC ICC ICC
Value
-0.5 to +7.0 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -40 to +85 -55 to +150 +4.75 to +5.25
Unit
Volts Volts Volts C C Volts
96
mA
50
mA
100060C
Conexant
4-5
4.0 Electrical and Mechanical Specifications
4.3 DC Characteristics
BT8110/8110B High-Capacity ADPCM Processor
4.3 DC Characteristics
All inputs in Table 4-6 have input thresholds compatible with TTL drive levels. Leakage current for each pin is less than 10 A in any state. All outputs have drive current IOL = +4 mA at 0.4 V and IOH = -4 mA at 2.4 V. All outputs are CMOS drive levels and can be used with CMOS or TTL logic.
Table 4-6. DC Characteristics Parameter
VDD VOH VOL VIH VIL IIL IOL CIN COUT
Description
Supply Voltage All Outputs, AD[6:0] All Outputs, AD[6:0] Input Voltage High Input Voltage Low Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance ESD Protection Latch-up Input
Conditions
Min
4.75
Typ
5.00 4.5 0.2 - - 1.0 1.0 - - >3 > 400 -
Max
5.25 - 0.45 - 1.35 10 10 10 10 - - 96 50
Units
Volts Volts Volts Volts Volts A A pF pF kVolts mA mA
IOH = -4 mA @ VDD = 4.5 V IOL = +4 mA @ VDD = 4.5 V VDD = 4.5 V VDD = 4.5 V 0V VIN VCC 0V VIN VCC Inputs and AD[6:0] All Outputs MIL-STD-883C, Method 3015 JEDEC JC-40.2 VDD = 5.0 V @ 8.192 MHz VDD = 5.0 V @ 8.192 MHz
2.2 3.15 - - - - - 2 150 -
BT8110: IDD BT8110B: IDD
Supply Current Supply Current
4-6
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
4.0 Electrical and Mechanical Specifications
4.4 Mechanical Specifications
4.4 Mechanical Specifications
Figure 4-3. 68-Pin Plastic Leaded Chip Carrier (J-Bend)
68 PLCC
D .042" X 45 .048" D1 .042" .056" SEE DETAIL 'A'
PIN 1 IDENTIFIER
.050" BSC.
D2 E2
E E1
D3 E3
D2 E2
A1 A
S Y M
INCHES
B O L
MILLIMETERS MAX. .200 .130 .995 .958 .465 .995 .958 .465 MIN. 4.20 2.29 25.02 24.13 11.30 25.02 24.13 11.30 20.32 REF. NOM. MAX. 5.08 3.30 25.27 24.33 11.81 25.27 24.33 11.81
.025"/.045" R
A A1 D D1 D2 D3 E E1 E2 E3
MIN. .165 .090 .985 .950 .445 .985 .950 .445
NOM.
.026" .032"
.800 REF.
20.32 REF.
.013" .021" .020" MIN.
.800 REF.
DETAIL "A"
100060_016
100060C
Conexant
4-7
4.0 Electrical and Mechanical Specifications
4.4 Mechanical Specifications
BT8110/8110B High-Capacity ADPCM Processor
4-8
Conexant
100060C
A
Appendix A. Hardware Mode Operation
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation
A.1.1 Introduction
This appendix details the BT8110/8110B ADPCM Processor 48- or 64-channel operation. This configuration may be used in conjunction with the Bt8200 ADPCM Line Formatter to build a 2:1 ADPCM transcoder. The interface nomenclature in Figure A-1 corresponds to that used with the T1 and E1 transcoder evaluation boards (Bt8200EVM-T1 and Bt8200EVM-E1). See Appendix D and E. Two BT8110/8110B 24- or 32-channel processors (combined with a single external ROM for the BT8110) will process either 48 or 64 full-duplex channels using interleaved encoder/decoder processing. This combination may also be programmed to alternately process 96 or 128 encode-only or decode-only channels.
A.1.2 Configuration
A block diagram showing the configuration of the BT8110/8110B for 48- or 64-channel operation is shown in Figure A-1. The two BT8110/8110Bs share all of the input and output signals and the external ROM to appear to external interfaces as a single functional device, and each takes turns reading the ROM to obtain the required outputs.
100060C
Conexant
A-1
Appendix A . Hardware Mode Operation
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation
BT8110/8110B
High-Capacity ADPCM Processor
Figure A-1. 48- or 64-Channel Configuration of the BT8110/8110B
CLOCK SYNC LAW 64 CHANNEL SERIAL_IN CNTRL CODE12 CODE13
CLOCK SYNC WR* AD[3] SERIAL_IN RESET, CS AD[4] AD[5] D[7:0] ADPCM Processor BT8110/8110B SERIAL_OUT A[13:0] SERIAL_OUT
External ROM CLOCK SYNC LAW 64 CHANNEL SERIAL_IN CNTRL CODE12 CODE13 CLOCK SYNC WR* AD[3] SERIAL_IN RESET, CS AD[4] AD[5] D[7:0]
ADPCM Processor BT8110/8110B A[13:0] SERIAL_OUT
100060_017
The two BT8110/8110Bs need to have the three mode control pins set to enable interleaved, encoder, or decoder modes; and processor number. In interleaved mode, the circuit will realize 48 or 64 full-duplex channels of ADPCM coding. In encoder mode, 96 or 128 encoders are realized. In decoder mode, 96 or 128 decoders are realized. To set the modes, the inputs AD[2], AD[1], and AD[0] need to be set as shown in Table A-1.
Table A-1. Mode Settings Pin Name
Interleaved Mode Encoder Mode Decoder Mode
Processor Number 1 AD[2] AD[1] AD[0]
001 001 010
Processor Number 2 AD[2] AD[1] AD[0]
010 011 000
Processor Number 1 and Processor Number 2 must be designated as such because, in this configuration, each BT8110/8110B responds to alternate groups of 16 clock cycles (12.288 or 16.384 MHz). The Number 1 and Number 2 designation is arbitrary and is not influenced by any other part of the circuitry.
A-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Appendix A . Hardware Mode Operation
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation
In addition, MICREN and PSIGEN must be held low if the serial inputs are used. However, the BT8110/8110B has a parallel signal input capability. If PSIGEN is connected to the supply voltage, the parallel signal input is enabled. Note that the CNTRL input is connected to both the RESET and the CS inputs (pins 20 and 22). The RESET input controls the algorithm reset function according to ANSI Standard T1.303-1989/ITU-T G.7.26 and the CS input controls transparency (the passthrough of the 8-bit input without encoding or decoding).
A.1.3 Functional Timing
Functional timing diagrams are given in Figure A-2 through Figure A-4 for interleaved operation, encoder-only operation, and decoder-only operation, respectively. The CLOCK signal has a frequency of 16.384 MHz for 64-channel full-duplex or 128-channel half-duplex operation, and 12.288 MHz for 48-channel or 96-channel half-duplex operation. The SYNC signal is used to identify channel 1 and is required at any multiple of 32 clock periods. Details of the timing are given in Chapter 4.0. For each mode, the channels are numbered. The numbers in parentheses are for 48-channel full-duplex operation or for 96-channel half-duplex (encoder- or decoder-only) operation.
Figure A-2. 48- or 64-Channel Full-Duplex Interleaved Mode Functional Timing
Ref. Cycle 16.384 (12.288) MHz CLOCK SYNC ADPCM_STB PCM_STB 8.192 (6.144) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-63 (47) RESET,CS PCM-0 SERIAL_OUT D[7:0] ADPCM-62 (46) D[7:0] Int (1) ADPCM-62 (46) PCM-61 (45) ADPCM-63 (47) PCM-61 (45) ADPCM-63 (47)
5 6 7 8 I1 I2 I3 I4 I5 S 2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
I1
I2
I3
I4
I5
S
2
3
4
5
6
7
8
I1
I2
I3
I4
I5
ADPCM-63 (47)
PCM-0 PCM-0 ADPCM-0
3 4 5
ADPCM-0 ADPCM-0
6
7
8
I1
I2
ADPCM-62 (46)
PCM-61 (45)
NOTE(S): (1) BT8110B only.
100060_018
100060C
Conexant
A-3
Appendix A . Hardware Mode Operation
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation
BT8110/8110B
High-Capacity ADPCM Processor
Figure A-3. 96- or 128-Channel Half-Duplex Encoder-Only Functional Timing
Ref. Cycle 16.384 (12.288) MHz CLOCK SYNC ADPCM_STB PCM_STB 8.192 (6.144) Mbit/s SERIAL_IN PSIG[7:0] PCM-127 (95) RESET,CS PCM-0 SERIAL_OUT D[7:0] ADPCM-124 (92) D[7:0] Int (1) ADPCM-124 (92) ADPCM-125 (93) ADPCM--126 (94) ADPCM-125 (93) ADPCM-126 (94)
I5 I1 I2 I3 I4 I5 I1 I2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S
2
3
4
5
6
7
8
S
2
3
4
5
6
7
8
S
2
3
4
5
6
PCM-127 (95)
PCM-0
PCM-1
PCM-0 PCM-1
I3 I4 I5
PCM-1
I1
I2
ADPCM-124 (92)
ADPCM-125 (93)
NOTE(S): (1) BT8110B only.
100060_019
A-4
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Appendix A . Hardware Mode Operation
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation
Figure A-4. 96- or 128-Channel Half-Duplex Decoder-Only Functional Timing
Ref. Cycle 16.384 (12.288) MHz CLOCK SYNC ADPCM_STB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PCM_STB 8.192 (6.144) Mbit/s SERIAL_IN PSIG[7:0] ADPCM-127 (95) RESET,CS ADPCM-0 SERIAL_OUT D[7:0] PCM-122 (90) D[7:0] Int (1) PCM-122 (90) PCM-123 (91) PCM-124 (92) PCM-123 (91) PCM-124 (92)
5 6 7 8 S 2 3 4 5 6 7 8 S 2 I1 I2 I3 I4 I5 I1 I2 I3 I4 I5 I1 I2 I3 I4 I5
ADPCM-127 (95)
ADPCM-0 ADPCM-0 ADPCM-1
3 4 5 6
ADPCM-1 ADPCM-1
7
8
S
2
PCM-122 (90)
ADPCM-123 (91)
NOTE(S): (1) BT8110B only.
100060_020
100060C
Conexant
A-5
Appendix A . Hardware Mode Operation
A.1 48- or 64-Channel Full-Duplex Hardware Mode Operation
BT8110/8110B
High-Capacity ADPCM Processor
A-6
Conexant
100060C
B
Appendix B. T1 Speech Compression
B.1 Introduction
This appendix details the operation of the BT8110/8110B ADPCM Processor with the Bt8300 Dual T1 Framer for application to speech compression. This operation mode can be used to provide full-duplex speech compression to 16, 24, 32, or 40 kbit/s using a variety of embedded and non-embedded codes. The BT8110/8110B provides the coding algorithms specified in ITU-T Recommendation G.726 and ANSI Standard T1.303-1989 at 40, 32, 24, or 16 kbit/s. It also provides the embedded codes in ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. The 32 kbit/s ADPCM algorithm is also specified in the AMIS version 1 digital messaging protocol. The speech compression application for 48 channels uses the Bt8300 with an associated 2 K x 8 RAM; two BT8110/8110Bs, (each with an associated 128 K ROM for the BT8110); and a microprocessor for configuration and control. Up to 14 separate coding algorithms can be selected by the microprocessor. An evaluation board is available for this configuration (part number Bt8113EVM). Although this application note and the Bt8113EVM both use the Bt8300 Dual T1 Framer (with external RAM), one or two Bt8360 Single T1 Framers (with internal RAM) can be used with one or two BT8110/8110Bs for 24 or 48 voice channels, respectively. The Bt8360 is a newer generation product and offers more voiceand signaling-related features than the Bt8300. For an even higher level of integration and functionality, a Bt8370 framer with integral LIU can be used.
B.1.1 Configuration
The configuration of the BT8110/8110B and the Bt8300 is shown in Figure B-1. The Bt8300 is used to transmit and receive two T1 lines. The slip buffers of the Bt8300 are used to synchronize the transmit and receive signals of both T1s for the BT8110/8110B.
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Appendix B . T1 Speech Compression
B.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
Figure B-1. T1 Speech Compression Interface Block Diagram
ADPCM Processor BT8110/8110B CLOCK PSIG[7:0] SYNC PSIGEN SERIAL_IN TX A CLK TX B CLK 1.544 CLK 12 MHz CLK TX SYNC B IN TX SYNC A OUT REC SLIP BUFF A TX PCM A REC SLIP BUFF B TX PCM B EXT ROM 8 SERIAL_OUT D[7:0] PSIG[0] ADPCM_STB PCM_STB
12.352 MHz Oscillator
8
PSIG (ADPCM Input) GND
D (ADPCM Output)
Dual T1 Framer Bt8300
ADPCM Processor BT8110/8110B CLOCK SYNC SERIAL_IN SERIAL_OUT PSIG[7:0] PSIGEN PSIG[0] D[7:0] 8 PSIG (ADPCM Input) GND ADPCM_STB PCM_STB
Microprocessor
EXT ROM
8
D (ADPCM Output)
100060_021
A single microprocessor can be used to control the Bt8300 and the two BT8110/8110Bs. The only requirement for the BT8110/8110B control is to configure the operating mode and the per-channel control registers that set the code rate and the A-law/-law, and reset the algorithm on each channel, as desired. The 12.352 MHz signal source required for the Bt8300 is also used for the BT8110 clock. To maintain proper synchronization of the BT8110/8110B, an exact 12.352 MHz source that is eight times the slip-buffer clock rate (which is the same as the transmit A PCM clock) must be used. This source can be phase-locked to one of the received clocks from the T1 line or to a local clock source. The slip-buffer clock and the transmit clock for the B side of the framer can then be obtained from the 1.544 MHz clock output from the Bt8300. If the 12.352 MHz clock source is not locked to the line, then the encoder buffer will have frame slips where one sample of PCM is either repeated or deleted before encoding to ADPCM. For speech signals, this impairment may be insignificant. The full-rate PCM inputs and outputs to the BT8110/8110B are serial and are configured to connect directly to the Bt8300. The SERIAL_IN and SERIAL_OUT signals of the BT8110/8110B connect directly to the slip buffer output and the transmit input of the framer, respectively. The frame synchronization is determined by the SYNC input, which can be obtained from
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High-Capacity ADPCM Processor
Appendix B . T1 Speech Compression
B.1 Introduction
the free-running synchronization signal TX SYNC A on the Bt8300 (this signal must also be connected to TX SYNC B IN to synchronize the B side transmitter). The BT8110/8110B clock of 6.144 MHz is obtained by internally dividing and gapping the 12.352 MHz input clock to the BT8110/8110B. The ADPCM inputs and outputs are timed by the signal ADPCM_STB. This signal will be identical at both BT8110/8110Bs. The input to each is applied to the parallel input PSIG[7:0], with the most significant bit at PSIG[7]. The output is obtained from the parallel signal output D[7:0], with the most significant bit at D[7]. The input data must be valid at the positive edge of ADPCM_STB and the output data is valid at the positive edge. Due to the processing delay of the BT8110/8110B, there is a five-channel offset between the timing of the ADPCM input and PCM output. The ADPCM output is always 5 bits or less (for 40 kbit/s coding and for all embedded codes). The ADPCM input includes up to 5 ADPCM input bits and 2 bits to indicate the number of bits in the decoder input when embedded encoding is used. The MICREN input must be connected to the supply voltage to enable the microprocessor interface. The PSIGEN pin must be held low. If the RESET input is not used to reset the algorithm externally, it should be held low; otherwise it should be generated. The RESET input is active high.
B.1.2 Functional Timing Diagram
The timing of the T1 speech compression interface circuit is given in Figure B-2. The clock signal is 12.352 MHz and is applied to the Bt8300 and both BT8110/8110Bs. The SYNC signal to the BT8110/8110B is the multiframe synchronization output of the Bt8300. This signal provides bit and channel synchronization to the BT8110/8110Bs. The SYNC signal has a period of 3 ms; the timing diagram shows the beginning of the frame at the end of the 3 ms period. The ADPCM_STB signal is an enable and clock output for the BT8110/8110Bs. Its positive edge occurs when the ADPCM input is clocked into the circuit and the ADPCM output is available from the ROM data pins. The frame-bit location can be identified from the wide interval on this signal, which occurs once per frame. The PCM serial input and output timing is determined by the Bt8300 synchronization. The two parts are designed so that as long as the clocks and synchronization signals are provided as shown in Figure B-1, the serial interface will operate properly. Each of the signals is clocked by the respective input circuitry near the middle of the signaling interval, so the interconnection circuitry is not critical. This makes it possible, for instance, to add drop-and-insert or other processing functions at the PCM interface.
NOTE:
The ADPCM inputs are taken from the parallel input PSIG[7:0] for the BT8110B, and PSIG[7:1] for the BT8110. The outputs are available on the ROM data output D[7:0] for the BT8110B, and D[7:1] for the BT8110. Note that encoding is provided for the timeslots that normally carry framing and signaling information.
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Appendix B . T1 Speech Compression
B.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
There is an offset in the timing between the input and the output signals caused by the processing delay of the BT8110/8110B. In Figure B-2, ADPCM-3 is the encoded output from PCM-3 and ADPCM-22 results in the decoded PCM-22. This offset must be accounted for in the processing for speech signals or can be eliminated by delaying the encoded output by 19 channel counts. If the RESET input pin is used to reset the ADPCM algorithm according to ANSI Standard T1.303-1989 and ITU-T G.726, the timing is as shown in the Figure B-2. Note that the RESET input has to be applied approximately 2 s before the corresponding ADPCM input; it is possible to use the PCM_STB signal to latch reset inputs for the ADPCM signal stream and the ADPCM_STB signal to latch reset inputs for the PCM input stream. In 48-channel designs, it may be helpful to have a single interleaved parallel bus. The signal PCM_STB, which is also an output from each BT8110/8110B, can be used to clock odd inputs and outputs on and off a single parallel bus.
Figure B-2. T1 Speech Compression Functional Timing Diagram
12.352 MHz CLOCK 6.176 MHz INT. CLK SYNC ADPCM_STB 1.544 Mbit/s SERIAL_IN 1.544 Mbit/s SERIAL_OUT PSIG[7:0] ADPCM-3 D[7:0] ADPCM-22 PCM_STB RESET PCM-1 D[7:0] Int (1) ADPCM-22 PCM-1 ADPCM-23 PCM-2 ADPCM-24 ADPCM-4 PCM-2 ADPCM-5 PCM-3 PCM-1 ADPCM-23 PCM-2 ADPCM-24 ADPCM-4 ADPCM-5
8 S 2 3 4 5 6 7 8 F S 2 3 4 5 6 7 8 S 2 3 4
PCM-24
8 S 2 3 4 5 6 7 8 S 2 3
PCM-1
4 5 6 7 8 S 2
PCM-2
3 4
PCM-24
PCM-1
PCM-2
NOTE(S): (1) BT8110B only.
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High-Capacity ADPCM Processor
Appendix B . T1 Speech Compression
B.1 Introduction
B.1.3 Microprocessor Interface And Per-Channel Configuration
The microprocessor interface of the Bt8300 provides all control and status functions for the T1 lines; it can also be used to insert and extract signaling in this application. Table B-1 lists the connections for the BT8110/8110B. Only 7 bits of the address/data bus are required. The BT8110/8110B can be operated by either an 8051-type or a 68HC11-type interface. Only the 8051-type connections are given here, since the Bt8300 requires this interface. The 68HC11 microprocessor can be used as well; two gates are required to derive the read and write control signals needed to emulate the 8051. The Bt8360 T1 Framer and the Bt8370 T1/E1 Framer/LIU interface directly with either the 8051-type or the 68HC11-type microprocessor.
Table B-1. BT8110/8110B Microprocessor Connection ADPCM Processor Pin
MICREN ALE WR* CS AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
Enable Address Latch Enable Write Enable Chip Select Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
Intel 8051
Vcc ALE WR* A-n AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Table B-2 lists the address map and the bit interpretations of the control fields. In this application address 0x40 must be set to a value of 0x14 to properly set the mode of the BT8110/8110B. A write to any address in the range 0x40-0x3F will cause the mode of the BT8110/8110B to be set. Table B-2 also provides the per-channel control register bit interpretations. Bits D[3:0] of each encoder and decoder channel control select the particular ADPCM code to be used; note that hex values of 6 and 7 are invalid for these bit positions. ROM codes are available from Conexant with the evaluation board. Bit D[6] enables A-law PCM coding when set. Bit D[5] enables the algorithm RESET function. This operation sets the internal parameters of the BT8110/8110B to fixed values, as specified in ANSI Standard T1.303-1989 and ITU-T G.726. Bit D[4] enables transparent operation. For the encoder channels, when the transparent bit is set all 8 PCM bits are transferred to the output with the same delay as when ADPCM encoding is taking place. Full 8-bit (64 kbit/s) transparent operation is not a valid option for the T1 speech compression interface configuration using the BT8110/8110B. 64 kbit/s transparent operation is valid with the BT8110/8110BB. For the decoder, the five ADPCM inputs and two embedded encoding inputs are transferred to the PCM
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High-Capacity ADPCM Processor
serial output with the same delay as when ADPCM decoding is taking place. The input to PSIG[0], the LSB, must be held at a logic low level in this application.
Table B-2. Microcontroller Memory Map Address (hex)
0 1 Interleaved Operation 2 * * * 0x3E 0x3F 0x40 0 Encoder/Decoder-Only Operation 1 2 * * * 0x3E 0x3F 0x40
Function
Encoder 0 Control Decoder 0 Control Encoder 1 Control * * * Encoder 31 Control Decoder 31 Control Mode Control Encoder/Decoder 0 Control Encoder/Decoder 1 Control Encoder/Decoder 2 Control * * * Encoder/Decoder 62 Control Encoder/Decoder 63 Control Mode Control
Bit
Mode Control Register D[2:0] D[3] D[4]
Function
Operation Mode 32/64-Channel Operation Serial PCM, Parallel ADPCM Mode
Encoder/Decoder Control Register
D[3:0] D[4} D[5] D[6]
Code Select (codes 6, 7 are invalid) Set Encoder/Decoder Transparent Reset Encoder/Decoder Set Encoder/Decoder to A-Law PCM
B-6
Conexant
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BT8110/8110B
High-Capacity ADPCM Processor
Appendix B . T1 Speech Compression
B.1 Introduction
Table B-3 shows the encoder and decoder locations for each PCM channel. This table is a cross-reference between the encoder and decoder addresses and the PCM channel timeslots.
Table B-3. BT8110/8110B Processor Per-Channel Control Locations PCM Channel
Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Channel 16 Channel 17 Channel 18 Channel 19 Channel 20 Channel 21 Channel 22 Channel 23 Channel 24
Encoder
00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E
Decoder
29 2B 2D 2F 01 03 05 07 09 0B 0D 0F 11 13 15 17 19 1B 1D 1F 21 23 25 27
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B.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
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Appendix C. E1 Speech Compression
C.1 Introduction
This appendix details of operation of the BT8110/8110B ADPCM Processor with the Bt8510 E1 Framer/LIU (or Bt8370 T1/E1 Framer/LIU) for application to speech compression. This mode can be used to provide full-duplex speech compression to 16, 24, 32, or 40 kbit/s using a number of embedded and non-embedded codes. The BT8110/8110B provides the coding algorithms specified in ITU-T Recommendation G.726 and ANSI Standard T1.303-1989 at 40, 32, 24, and 16 kbit/s. It also provides the embedded codes in ITU-T Recommendation G.727 and ANSI Standard T1.310-1991. The 32 kbit/s ADPCM algorithm is also used in the AMIS version 1 digital messaging protocol. The speech compression application for 30 channels requires a Bt8510 E1 Framer circuit, a BT8110/8110B (with an associated 128 K ROM for the BT8110), and a microprocessor for configuration and control. Up to 14 separate coding algorithms can be selected by the controller on a channel-by-channel basis. This application requires approximately 20 square inches and approximately 1.5 Watts of power from a +5 V supply.
C.1.1 Configuration
Figure C-1 illustrates a configuration of the BT8110/8110B and the Bt8510. The Bt8510 transmits and receives a digital line at the 2.048 Mbit/s primary rate. The slip buffer of the Bt8510 frame-synchronizes the receive signal to the transmit signal so that the BT8110/8110B can operate synchronously on both signals. A single microprocessor can be used to control the Bt8510 and the BT8110/8110B. The only control requirement of the microprocessor is to configure the operating mode and the per-channel control registers that set the code rate and reset the algorithm on each channel, as desired. The Bt8510 and the BT8110/8110B each have a chip select input that can be used to select the desired device. The Bt8510 includes an integral digital timing recovery circuit and analog interface that is compatible with either 75 cable or 120 twisted-pair wire and meets the requirements of ITU-T Recommendation G.703. The timing recovery circuit requires a 32.768 MHz clock signal. The Bt8510 provides a 16.384 MHz output which can be divided by 2 to provide the 8.192 MHz clock required by the BT8110/8110B and can also be provided to the system clock input.
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Appendix C . E1 Speech Compression
C.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
A 2.048 MHz bit clock is then provided at BITCKO. This bit clock is used as the clock input to both the transmitter circuit and the slip buffer circuit. This procedure ensures proper alignment of the BT8110/8110B bit and system clocks.
Figure C-1. E1 Speech Compression Interface Configuration
32.768 MHz VCXO
CK160 SYSCKI SLPSYNCI XYSNCO SLPPCMO E1 Framer Bt8510 XPCMI BITCKO XCKI SLPCKI XSYNCI
/2
CLOCK
PSIG[7:0]
8
ADPCM_Input ADPCM_STB PCM_STB +5 V
SYNC SERIAL_IN SERIAL_OUT A[13:0]
ADPCM Processor BT8110/B
MICREN RESET PSIGEN PSIG[0]
D[7:0]
EXT ROM
8
D (ADPCM Output)
Microprocessor
100060_023
If the 32.768 MHz signal source is then phase-locked to the received clock (by phase-locking the slip buffer sync output to the receive sync output) then the transmit and receive clocks will be synchronized and no frame slips will appear at the receiver. The full-rate PCM inputs and outputs to the BT8110/8110B are serial and are configured to connect directly to the Bt8510. The SERIAL_IN and SERIAL_OUT signals of the BT8110/8110B connect directly to the slip buffer output and the transmit input of the framer, respectively. The BT8110/8110B frame synchronization is determined by the SYNC input, which can be obtained from the free-running synchronization signal XSYNCO from the Bt8510 (this signal must also be connected to SLPSYNCI to synchronize the receive slip buffer). The ADPCM inputs and outputs are timed by the signal ADPCM_STB. The input to the BT8110/8110B is applied to the parallel input PSIG[7:0], with the most significant bit at PSIG[7]. The output is obtained from the ROM data bus D[7:0], with the most significant bit at D[7]. The input data must be valid at the positive edge of ADPCM_STB and the output data is valid at the positive edge. Due to the processing delay of the BT8110/8110B, there is a five-channel offset between the timing of the ADPCM input and output. The ADPCM output is always 5 bits (for 40 kbit/s coding and for all embedded codes) or less. The input includes up to 5 ADPCM input bits and 2 bits to indicate the number of bits in the decoder input when embedded encoding is used.
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High-Capacity ADPCM Processor
Appendix C . E1 Speech Compression
C.1 Introduction
The MICREN input must be connected to the supply voltage to enable the microprocessor interface. The PSIGEN pin must be held at a logic low level. If the RESET input is not used to reset the algorithm externally, it should be connected to ground as shown in Figure C-1; otherwise it should be generated. The RESET input is active high.
C.1.2 Functional Timing Diagram
Figure C-2 illustrates the timing of the BT8110/8110B circuit. The CLOCK signal is 8.192 MHz and is applied to the BT8110/8110B. The SYNC signal to the BT8110/8110B is the multiframe synchronization output of the Bt8510. This signal provides channel synchronization to the BT8110/8110B. The SYNC signal has a period of 2 ms; the timing diagram shows the beginning of the frame at the end of the 2 ms period. The ADPCM_STB signal is an enable and clock output for the BT8110/8110B. Its positive edge occurs when the ADPCM input is clocked into the circuit and the ADPCM output is available from the ROM data pins. The PCM serial input and output timing is determined by the Bt8510 synchronization. The two parts are designed so that as long as the clocks and synchronization signals are provided as shown in Figure C-1, the serial interface will operate properly. Each of the signals is clocked by the respective input circuitry near the middle of the signaling interval, so the interconnection circuitry is not critical. This makes it possible to add drop-and-insert or other processing functions at the serial PCM interface.
NOTE:
The ADPCM inputs are taken from the parallel input PSIG[7:0] for the BT8110B, and PSIG[7:1] for the BT8110. The outputs are available on the ROM data output D[7:0] for the BT8110B, and D[7:1] for the BT8110. Note that encoding is provided for the timeslots that normally carry framing and signaling information.
There is an offset in the timing between the input and the output signals caused by the processing delay of the BT8110/8110B. In Figure C-2, ADPCM-3 is the encoded output from PCM-3 and ADPCM-30 results in the decoded PCM-30. This offset must be accounted for in the processing for speech signals, or can be eliminated by delaying the encoded output by 27 channel counts. If the RESET input pin is used to reset the ADPCM algorithm according to ANSI Standard T1.303-1989 and ITU-T G.726, the timing is as shown in the Figure C-2. Note that the RESET input has to be applied approximately 2 s before the corresponding ADPCM input; it is possible to use the PCM_STB signal to latch reset inputs for the ADPCM signal stream and the ADPCM_STB signal to latch reset inputs for the PCM input stream.
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C.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
Figure C-2. E1 Speech Compression Functional Timing Diagram
8.192 MHz CLOCK SYNC ADPCM_STB 2.048 Mbit/s SERIAL_IN 2.048 Mbit/s SERIAL_OUT PSIG[7:0], CODE[1,0], OPT, EMB D[7:0] ADPCM-29 PCM_STB RESET PCM-0 D[7:0] Int (1) ADPCM-29 PCM-0 ADPCM-30 PCM-1 ADPCM-31 ADPCM-3 PCM-1 ADPCM-4 PCM-2 PCM-0 ADPCM-30 PCM-1 ADPCM-31
8
8
S
2
3
4
5
6
7
8
S
2
3
4
5
6
7
8
S
2
3
4
5
PCM-31 (Frame 15)
S 2 3 4 5 6 7 8 S 2
PCM-0 (Frame 0)
3 4 5 6 7 8 S 2
PCM-1
3 4 5
PCM-31
PCM-0
PCM-1
ADPCM-2
ADPCM-3
ADPCM-4
NOTE(S): (1) BT8110B only.
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High-Capacity ADPCM Processor
Appendix C . E1 Speech Compression
C.1 Introduction
C.1.3 Microprocessor Interface and Per-Channel Configuration
The microprocessor interface of the Bt8510 provides all control and status functions for the E1 lines; it can also be used to insert and extract signaling in this application. The connections for the BT8110/8110B are given in Table C-1. Only 7 bits of the address/data bus are required. Any one of the six upper address bits, A[13:8], of the microprocessor can be used as a chip select signal. The BT8110/8110B can be operated by either a 8051-type or a 68HC11-type interface. Only the 8051-type connections are given in Table C-1. For the 68HC11, the E signal must be connected to WR* and the AS signal to ALE. The other connections are the same.
Table C-1. BT8110/8110B Microprocessor Connection ADPCM Processor Pin
MICREN ALE WR* CS AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Function
Enable Address Latch Enable Write Enable Chip Select Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
Intel 8051
Vcc ALE WR* A[n] AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6]
Table C-2 gives the address map and the bit interpretations of the control fields. In this application address 0x40 must be set to a value of 0x1C to properly set the mode of the BT8110/8110B. A write to address 0x40 will cause the mode of the BT8110/8110B to be set. At least 750 ns must be allowed between consecutive write operations to the BT8110/8110B. Table C-2 also provides the Per-Channel Control Register bit interpretations. Bits D[3:0] of each encoder and decoder channel control select the particular ADPCM code to be used; note that hex values of 6 and 7 are invalid for these bit positions. ROM codes are available from Conexant. Bit D[6] enables A-law PCM coding when set to 1. Bit D[5] enables the algorithm RESET function when set to 1. This operation sets the internal parameters of the BT8110/8110B to fixed values, as specified in ITU-T Recommendation G.726 and ANSI Standard T1.303. Bit D[4] enables transparent operation when set to 1. For the encoder channels, when the transparent bit is set, all 8 PCM bits are transferred to the output with the same delay as when ADPCM decoding is taking place. For the decoder, the five ADPCM inputs and two embedded-encoding inputs are transferred to the PCM serial output with the same delay as when ADPCM decoding is taking place. On the BT8110 only, the input to PSIG[0], the least significant bit, must be held at a logic low level in this application (this pin has an internal pull-down resistor).
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Appendix C . E1 Speech Compression
C.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
Table C-2. BT8110/8110B Microprocessor Memory Map Address
0 1 Interleaved Operation 2 * * * 0x3E 0x3F 0x40 0 Encoder/Decoder-Only Operation 1 2 * * * 0x3E 0x3F 0x40
Function
Encoder 0 Control Decoder 0 Control Encoder 1 Control * * * Encoder 31 Control Decoder 31 Control Mode Control Encoder/Decoder 0 Control Encoder/Decoder 1 Control Encoder/Decoder 2 Control * * * Encoder/Decoder 62 Control Encoder/Decoder 63 Control Mode Control
Bit
Mode Control Register D[2:0] D[3] D[4] D[3:0] D[4] D[5] D[6]
Function
Operation Mode: 100 - Low speed, Interleaved 32/64-Channel Operation: Set to 1 Serial PCM, Parallel ADPCM Mode: Set to 1 Code Select (codes 6, 7 are invalid) Set Encoder/Decoder Transparent Reset Encoder/Decoder Set Encoder/Decoder to A-Law PCM
Encoder/Decoder Control Register
C-6
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High-Capacity ADPCM Processor
Appendix C . E1 Speech Compression
C.1 Introduction
Table C-3 gives the encoder and decoder locations for each PCM channel control word. This table is a cross-reference between the encoder and decoder addresses and the PCM channel timeslots.
Table C-3. BT8110/B Per-Channel Control Locations PCM Timeslot
Timeslot 0 Timeslot 1 Timeslot 2 Timeslot 3 Timeslot 4 Timeslot 5 Timeslot 6 Timeslot 7 Timeslot 8 Timeslot 9 Timeslot 10 Timeslot 11 Timeslot 12 Timeslot 13 Timeslot 14 Timeslot 15 Timeslot 16 Timeslot 17 Timeslot 18 Timeslot 19 Timeslot 20 Timeslot 21 Timeslot 22 Timeslot 23 Timeslot 24 Timeslot 25 Timeslot 26 Timeslot 27 Timeslot 28 Timeslot 29 Timeslot 30 Timeslot 31
Encoder
00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E
Decoder
39 3B 3D 3F 01 03 05 07 09 0B 0D 0F 11 13 15 17 19 1B 1D 1F 21 23 25 27 29 2B 2D 2F 31 33 35 37
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C.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
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D
Appendix D. T1 ADPCM Transcoder
D.1 Introduction
This appendix describes an assembly of the BT8110/B ADPCM Processor, Bt8200 ADPCM Line Formatter, and Bt8300 (dual), Bt8360 (single) T1 Clear-Channel Framers, or the Bt8370 T1/E1 Framer/LIU that realizes a single-board transcoder meeting the interface requirements given in ANSI Standard T1.302-1989. An evaluation board is available for this configuration (Bt8200EVM-T1). T1.302-1989 is a line format standard for 32 kbit/s ADPCM compression of voice-band signals. It specifies three signaling methods for transcoders: * * Bundle Format--Provides 44 voice-band channels in a T1 along with four signaling and alarm overhead channels. Transition Signaling--Provides 48 channels with 32 kbit/s ADPCM and allows the switching of ADPCM in DS0s in DCS systems and network managers and is thus compatible with fractional T1 services. Robbed-Bit Signaling--Provides 48 channels with 32 kbit/s and with 24 kbit/s used every sixth frame to provide bandwidth for signaling bits. T1.303-1989/G.726 specifies the 24-kbit/s ADPCM algorithm used for signaling frames.
*
D.1.1 Description
A transcoder meeting the requirements of these standards and providing the option of all three methods of signaling can be developed with three Conexant products: BT8110/B, Bt8200, Bt8300 (or Bt8360 or Bt8370 in place of Bt8300). Two BT8110/Bs provide transcoding for 48 channels; the code rate can be adjusted from 32 kbit/s to 24 kbit/s on a channel-by-channel, frame-by-frame basis. The Bt8200 buffers and synchronizes the transcoded PCM and ADPCM signals to obtain the required line formats and translates the signaling bits as required. Three T1 framers are used. Two T1 framers synchronize the X and Y (PCM) T1 ports; a third T1 framer provides frame synchronization and frame generation for the Z interface that carries the compressed voice channels at 32 kbit/s.
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Appendix D . T1 ADPCM Transcoder
D.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
Figure D-1 shows the transcoder assembly. Circuit elements required include a microprocessor; a 12.352 MHz timing oscillator that can be synchronized to any of the T1 signals or synchronized externally; T1 line interface units, used to generate and recover pulses to and from the T1 lines; and an optional RS-232C interface to a supervisory data link.
Figure D-1. Single-Board Transcoder Assembly
UART Link
RS-232C T1 LIU
X
Microcontroller
Bt8300 (or 2 Bt8360s, Bt8370s) X PORT Dual T1 Framer Y PORT
Bt8200 Z PORT
Bt8300 (or Bt8360, Bt8370) TI Framer T1 LIU Z
ADPCM Line Formatter
Y
T1 LIU
ADPCM Processors BT8110/B
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The microprocessor sets the configuration of the transcoder and monitors all status and alarm indications. It can also send and receive messages on all of the T1 ESF data links, as required. Optional status (LED) indicators can also be set by the microprocessor. The UART link to the RS-232C interface can be used to transfer supervisory signaling to and from the Bt8200 ports, to set idle and transparent (uncoded PCM or data) channels, and to provide the optional templates for bundle transmission in AT&T PUB 54070 and Bellcore TR-TSY-000210. The ADPCM processor consists of two 68-pin PLCC integrated circuits (and a 128 K ROM for the BT8110). The Bt8300 consists of an 84-pin PLCC and an external 2 K x 8 RAM; Bt8360 is a 68-pin PLCC with internal RAM; Bt8370 is an 80-pin PLCC with internal RAM and integral LIU; and Bt8200 consists of an 84-pin PLCC integrated circuit and an external 8 K x 8 RAM. The microprocessor can be provided by several different configurations, but typically an Intel 8051-family part and program memory are used. Only a +5 V supply is required; power consumption of the assembly totals less than 3.0 Watts. The entire transcoder can be put in approximately 30 square inches (194 square centimeters) of circuit-board area, allowing for the development of a single-board wall-mount unit. The compact size and low power consumption also permits the development of built-in units for channel banks and customer-premise multiplexers. An evaluation board for the transcoder configuration is available. This board uses two BT8110/Bs, one Bt8200, and three Bt8360s. The microprocessor is programmed to obtain maintenance and status information, to set up template configurations, and to perform the diagnostic tests on the BT8110/Bs.
D-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Appendix D . T1 ADPCM Transcoder
D.1 Introduction
D.1.2 Summary
The transcoder assembly can be used to double the voice-channel capacity of a T1 line, as shown in Figure D-2. The full-rate T1s can come from DCS systems, channel banks, PBXs, or other T1 PCM stream signal sources. The ADPCM transcoder can be used to interface AT&T's M44 multiplexing service when the bundle format is used. When transition signaling is used, all 48 channels are provided. Also, transition signaling is compatible with all fractional T1 services. A software listing of the program used by the Bt8200EVM-T1 is available upon request.
Figure D-2. Single-Board Transcoder Application
T1 X Transcoder Z T1 Y X Z Transcoder Y T1
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32 Kbit/s ADPCM T1
T1
100060C
Conexant
D-3
Appendix D . T1 ADPCM Transcoder
D.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
D.1.3 ADPCM Transcoder System Specifications
Table D-1. ADPCM Transcoder System Specifications Name
Channel Capacity ADPCM Coding 48 channels, full-duplex. Per ANSI Standard T1.303-1989 and ITU-T G.726 @ 32 kbit/s for bundle format and transition signaling and 32 kbit/s and 24 kbit/s for robbed-bit signaling. Both ANSI standard and proprietary robbed-bit signaling algorithms are supported. Bundle format or transition signaling per ANSI Standard T1.302-1989 on per 384 kbit/s (bundle) basis. Robbed-bit signaling per ANSI Standard T1.302.1989. SF, ESF, SLC(R) 96 are options on all T1s. ZBTSI and/or B8ZS can be selected via processor control or auto-selected based on far-end format. Both bit-oriented and message-oriented signaling supported on X, Y, and Z ports. Via built-in 4.8 kbit/s serial port or X, Y, or Z ESF data link to integral microprocessor. X, Y, and Z T1 outputs synchronized to any received T1 or to external timing reference. All T1, bundle, and transition signaling alarms available via microprocessor. Indicators provided as required. Looping of each T1 available via microprocessor control. T1 PCM channels can be selected as transparent on 32 kbit/s boundaries. This allows transmission of digital data in increments of 32 kbit/s. Full-time in-service diagnostic test of ADPCM coding processor for all channels using idle channel or channel used for bundle delta channel. Storage of configuration data during power outage in nonvolatile EEROM memory. Per-channel optional insertion of selectable PCM code and signaling states on all idle channels. 0-250 s on X, Y, and Z ports. Less the 3.0 Watts per system Approximately 5" x 8" (12.7 cm x 20.3 cm).
Description
Signaling Modes
T1 Framing T1 Clear Channel T1 ESF Data Link Configuration Control Synchronization Alarms T1 Self-Test Transparent Channels
Diagnostic Test
Program Storage Idle Channel Control Slip Buffer Power Requirement Board Dimensions
D-4
Conexant
100060C
E
Appendix E. E1 ADPCM Transcoder
E.1 Introduction
This appendix describes an assembly of the BT8110/B ADPCM Processor, Bt8200 ADPCM Line Formatter, and Bt8510 E1 Framer or the Bt8370 T1/E1 Frame/LIU that realizes a single-board transcoder meeting the transcoding requirements of ITU-T Recommendation G.726 and the interface requirements given in ITU-T Recommendation G.761. An evaluation board is available for this configuration (Bt8200EVM-E1). G.726 is a transcoding algorithm between 64 kbit/s PCM and 32 kbit/s ADPCM. G.761 is a line format for 32 kbit/s ADPCM compression of voice-band signals on 2.048 Mbit/s primary-rate digital streams. Signaling conversion from the full-rate source streams to the compressed digital stream is specified in G.761 as well. This signaling conversion requires processing of signaling history with a scrambling algorithm to ensure that no multiframe alignment signal emulation can occur on the compressed E1 stream.
E.1.1 Description
The Bt8200EVM-E1 transcoder meeting the requirements of G.761 was developed with three Conexant products: BT8110/B, Bt8200, Bt8510. Two BT8110/B ADPCM processors provide transcoding for 60 channels. Two Bt8200 ADPCM Line Formatters buffer and synchronize the encoded and decoded ADPCM and PCM signals, respectively, to obtain the required line formats. Three Bt8510 E1 Framers are used, one each for the full-rate A and B ports and one for the compressed C port. Figure E-1 shows the transcoder assembly. Circuit elements required include a microprocessor; two 16.384 MHz timing oscillators that can be synchronized to any of the E1 signals or synchronized externally; and an optional RS-232C interface to a supervisory data link. The encoder and the decoder operate with separate time bases; normally the decoder is synchronized to the incoming clock at the C port to meet the synchronization requirements of G.761. The microprocessor sets the configuration of the transcoder and monitors all status and alarm indications. Optional status (LED) indicators can also be set by the microprocessor. The UART link to the RS-232C interface can be used to transfer supervisory signaling to and from the Bt8200 ports, to set idle and transparent (uncoded PCM or data) channels, to provide the signaling conversion (G.761 signaling performed by microprocessor or external hardware) between the
100060C
Conexant
E-1
Appendix E . E1 ADPCM Transcoder
E.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
full-rate and compressed ports required by G.761, and to enter, implement, and monitor diagnostic tests of the BT8110/B. The Bt8510 E1 framers include analog line interfaces that are compatible with 75 cable or 120 wire-pair lines, a digital timing-recovery circuit, and slip buffers. This allows the circuit set to provide all termination and synchronization functions required for transcoding. The ADPCM processors operate on a time-shared-logic principle, so that all circuit elements are shared by all channels. This characteristic makes it possible to provide a full-time diagnostic test of both BT8110/Bs on the framing and signaling timeslots without disturbing active traffic.
Figure E-1. Single-Board Transcoder Assembly
RS-232C
UART Link
BT8110/B ADPCM Processor
Microprocessor Bt8200 Bt8510 A E1 Framer/LIU ADPCM Line Formatter E1 Framer/LIU
Bt8200
C
B
E1 Framer/LIU
ADPCM Line Formatter
BT8110/B
ADPCM Processor
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Each ADPCM processor consists of a 68-pin PLCC integrated circuit (and a 128 K ROM for the BT8110). Each Bt8510 consists of a 68-pin PLCC circuit. Each Bt8200 consists of an 84-pin PLCC integrated circuit and an 8 K x 8 RAM. The microprocessor can be provided by several different configurations, but a typical configuration includes an Intel 80C188 processor and program memory. Only a +5 V supply is required; power consumption of the assembly totals less than 4 Watts. The entire transcoder can be put in approximately 40 square inches (260 square centimeters) of circuit-board area, allowing for the development of a single-board wall-mount unit. The compact size and low power consumption also permits the development of built-in units for channel banks and customer-premise multiplexers. An evaluation board constructed in this configuration is available. The microprocessor is programmed to obtain maintenance and status information, provide the signaling conversion between the full-rate and compressed E1 streams, and to perform diagnostic tests of the BT8110/Bs. A software listing of the program used by the Bt8200EVM-E1 is available upon request.
E-2
Conexant
100060C
BT8110/8110B
High-Capacity ADPCM Processor
Appendix E . E1 ADPCM Transcoder
E.1 Introduction
E.1.2 Summary
The transcoder assembly can be used to double the voice-channel capacity of an E1 line, as shown in Figure E-2. The full-rate E1s can come from DCS systems, channel banks, PBXs, or other E1 PCM stream signal sources.
Figure E-2. Single-Board Transcoder Application
E1 A Transcoder C E1 A A C Transcoder B E1
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32 Kbit/s ADPCM E1
E1
E.1.3 ADPCM Transcoder System Specifications
Table E-1. ADPCM Transcoder System Specifications Name
Channel Capacity ADPCM Coding Signaling Modes E1 Framing Line Interface Unit Configuration Control Synchronization
Description
60 channels, full-duplex. 32 kbit/s ADPCM per ITU-T Recommendation G.726. Signaling per ITU-T Recommendation G.761. Per ITU-T Recommendation G.704, G.706, G.732. Integral analog line interface unit Bt8510 E1 Framer. Via built-in 4.8 kbit/s serial port. A and B E1 outputs synchronized to received C E1. C E1 output synchronized to A, B, or C input or to external timing reference. All E1 alarms available via microprocessor. Indicators provided as required. Looping of each E1 available via microprocessor control. E1 PCM channels can be selected as transparent according to requirements of recommendation G.761. Full-time in-service diagnostic test of ADPCM processor for all channels using timeslot 0 and timeslot 16. Storage of configuration data during power outage in nonvolatile EEROM or NOVRAM memory. Per-channel optional insertion of selectable PCM code and signaling states on all idle channels. 0-250 s on A, B, and C ports. Less then 4 Watts per system @ 4.75-5.25 Volts. Approximately 5" x 8" (12.7 cm x 20.3 cm).
Alarms E1 Self-Test Transparent Channels Diagnostic Test Program Storage Idle Channel Control Slip Buffer Power Requirement Board Dimensions
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Conexant
E-3
Appendix E . E1 ADPCM Transcoder
E.1 Introduction
BT8110/8110B
High-Capacity ADPCM Processor
E-4
Conexant
100060C
0.0 Sales Offices
Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 Phone: (82 53) 745 2880 Fax: (82 53) 745 1440
World Headquarters
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Japan Headquarters
Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 JAPAN Phone: (81 3) 5371-1567 Fax: (81 3) 5371-1501
APAC Headquarters
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